ICS 252 Introduction to Computer Design Lecture 12 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.

Slides:



Advertisements
Similar presentations
The Primal-Dual Method: Steiner Forest TexPoint fonts used in EMF. Read the TexPoint manual before you delete this box.: AA A A AA A A A AA A A.
Advertisements

Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
1 NP-completeness Lecture 2: Jan P The class of problems that can be solved in polynomial time. e.g. gcd, shortest path, prime, etc. There are many.
ECE Synthesis & Verification 1 ECE 667 Synthesis and Verification of Digital Systems Formal Verification Combinational Equivalence Checking.
1 Steiner Tree on graphs of small treewidth Algorithms and Networks 2014/2015 Hans L. Bodlaender Johan M. M. van Rooij.
Winter 2005ICS 252-Intro to Computer Design ICS 252 Introduction to Computer Design Lecture 5-Scheudling Algorithms Winter 2005 Eli Bozorgzadeh Computer.
Advanced Data Structures
ECE 667 Synthesis and Verification of Digital Systems
CS 151 Digital Systems Design Lecture 11 NAND and XOR Implementations.
© 2006 Pearson Addison-Wesley. All rights reserved14 A-1 Chapter 14 Graphs.
Technology Mapping.
Technology Mapping 2 Outline Goal Reading Tree Pattern Matching
ENGIN112 L11: NAND and XOR Implementation September 26, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 11 NAND and XOR Implementations.
ECE Synthesis & Verification - L211 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Verification Equivalence checking.
Boolean Matching in Logic Synthesis. Equivalence of Functions Equivalence of two functions defined under l Negation of input variables l Permutation of.
Taylor Expansion Diagrams (TED): Verification EC667: Synthesis and Verification of Digital Systems Spring 2011 Presented by: Sudhan.
Technology Mapping 1 Outline –What is Technology Mapping? –Rule-Based Mapping –Tree Pattern Matching Goal –Understand technology mapping –Understand mapping.
EDA (CS286.5b) Day 19 Covering and Retiming. “Final” Like Assignment #1 –longer –more breadth –focus since assignment #2 –…but ideas are cummulative –open.
COE 561 Digital System Design & Synthesis Library Binding Dr. Muhammad Elrabaa Computer Engineering Department King Fahd University of Petroleum & Minerals.
ECE Synthesis & Verification - Lecture 4 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Allocation:
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
ICS 252 Introduction to Computer Design
ECE Synthesis & Verification - Lecture 10 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Binary.
ECE 667 Synthesis and Verification of Digital Systems
ICS 252 Introduction to Computer Design Multi-level Logic Optimization Fall 2006 Eli Bozorgzadeh Computer Science Department-UCI.
Technology Mapping Outline Goal What is Technology Mapping?
ECE Synthesis & Verification, Lecture 17 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Technology.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
Overview Part 1 – Design Procedure 3-1 Design Procedure
Important Problem Types and Fundamental Data Structures
Logic Decomposition ECE1769 Jianwen Zhu (Courtesy Dennis Wu)
Graph Algorithms Using Depth First Search Prepared by John Reif, Ph.D. Distinguished Professor of Computer Science Duke University Analysis of Algorithms.
CSCI-455/552 Introduction to High Performance Computing Lecture 18.
Fixed Parameter Complexity Algorithms and Networks.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 12 – Design Procedure.
COE4OI5 Engineering Design. Copyright S. Shirani 2 Course Outline Design process, design of digital hardware Programmable logic technology Altera’s UP2.
Combinatorial Algorithms Unate Covering Binate Covering Graph Coloring Maximum Clique.
Combinational Logic Design BIL- 223 Logic Circuit Design Ege University Department of Computer Engineering.
CSCE350 Algorithms and Data Structure Lecture 17 Jianjun Hu Department of Computer Science and Engineering University of South Carolina
VLSI Backend CAD Konstantin Moiseev – Intel Corp. & Technion Shmuel Wimer – Bar Ilan Univ. & Technion.
Zvi Kohavi and Niraj K. Jha 1 Multi-level Logic Synthesis.
MA/CSSE 473 Day 15 BFS Topological Sort Combinatorial Object Generation Intro.
Combinational Problems: Unate Covering, Binate Covering, Graph Coloring and Maximum Cliques Example of application: Decomposition.
ICS 252 Introduction to Computer Design Lecture 9 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 3 – Combinational Logic Design Part 1 –
CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 4: Logic Optimization Chapter 4.
Kuo-Hua Wang, Chung-Ming Chan, Jung-Chang Liu Dept. of CSIE Fu Jen Catholic University Slide: Chih-Fan Lai Simulation and SAT-Based Boolean Matching for.
1 Technology Mapping Example: t t 1 = a + bc; t 2 = d + e; t 3 = ab + d; t 4 = t 1 t 2 + fg; t 5 = t 4 h + t 2 t 3 ; F = t 5 ’; This shows an unoptimized.
Data Structures and Algorithms in Parallel Computing Lecture 2.
Technology Mapping. 2 Technology mapping is the phase of logic synthesis when gates are selected from a technology library to implement the circuit. Technology.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Multi-Level Logic Synthesis.
Logic synthesis flow Technology independent mapping –Two level or multilevel optimization to optimize a coarse metric related to area/delay Technology.
BDDs1 Binary Tree Representation The recursive Shannon expansion corresponds to a binary tree Example: Each path from the root to a leaf corresponds to.
Combinational Logic Design. 2 Combinational Circuits A combinational logic circuit has: ♦ A set of m Boolean inputs, ♦ A set of n Boolean outputs ♦ n.
ICS 252 Introduction to Computer Design Lecture 8 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
Chapter 11. Chapter Summary  Introduction to trees (11.1)  Application of trees (11.2)  Tree traversal (11.3)  Spanning trees (11.4)
Presented By Anna Fariha Roll : SN – 213 MS, 1 st Semester Session: Boolean Matching.
Reducing Structural Bias in Technology Mapping
Overview Part 1 – Design Procedure Part 2 – Combinational Logic
ICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design
Reconfigurable Computing
ICS 252 Introduction to Computer Design
Chapter 3 – Combinational Logic Design
Sungho Kang Yonsei University
ECE 667 Synthesis and Verification of Digital Systems
ICS 252 Introduction to Computer Design
Technology Mapping I based on tree covering
VLSI CAD Flow: Logic Synthesis, Placement and Routing Lecture 5
Presentation transcript:

ICS 252 Introduction to Computer Design Lecture 12 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI

2 Winter 2004ICS 252-Intro to Computer Design Cell-Library Binding Task of transforming an unbound logic network into a bound network Bound network: interconnection of components that are instances of elements of a given library Interface to physical design Technology-dependent optimization Referred to as technology mapping as well.

3 Winter 2004ICS 252-Intro to Computer Design Library binding Library: set of logic primitives Binding process: exploit the library for best implementation Optimize: area/delay/testability Optimization tasks: intractable Two groups –Heuristics –Rule-based

4 Winter 2004ICS 252-Intro to Computer Design Library binding Digital circuits: hierarchical and sequential in nature Registers, input/output binding: direct replacement Binding on multi-level combinational components Library cells: single output combinational cells Two level logics are decomposed into multi-level before library binding (except for PLA implementation)

5 Winter 2004ICS 252-Intro to Computer Design vxvx b c vwvw vuvu e f vyvy d vzvz d b c e f d d b c e f d d b c e f d d

6 Winter 2004ICS 252-Intro to Computer Design Problem Formulation Element in library –Characterized by function, terminals, and parameters such as area, delay, etc. Single-output combinational logic function An area cost input-/output propagation delay Common approach: network covering –Replacing subnetwork with cell library –Cell matches a subnetwork if they are functionally equivalent –A necessary condition is that each internal vertex is covered by at least one match.

7 Winter 2004ICS 252-Intro to Computer Design Covering problem in library binding Librarycost AND2 OR2 OA v1v1 b c v2v2 v3v3 d a a b c d a b c d m4 m3 m1:OR2 m2:AND2 m3:AND2 a b c d

8 Winter 2004ICS 252-Intro to Computer Design Covering problem example V1 can be covered by unate clause m1+m4+m5 V2 can be covered by clause m2+m4 V3 can be covered by clause m3+m5 Ensure that appropriate inputs are available to each chosen (matched) cell. –m2  m1 by binate clause m’2+m1 –m3  m1 by clause m’3+m1  (m1+m4+m5)(m2+m4)(m3+m5)(m’2+m1)(m’3+m1)=1 Binate clause  binate covering  intractable problem

9 Winter 2004ICS 252-Intro to Computer Design Algorithms for library binding Library binding similar to code generation in a software compiler –Matching problem addresses generation of possible substitutions –Covering problem gives optimal selection of matches Network binding problem Matching on network –Boolean –Structural

10 Winter 2004ICS 252-Intro to Computer Design Matching of two scalar combinational functions Boolean matching –Given two single-output combinational functions f(x) and g(y), we say f matches g if there exists a permutation matrix P such that f(x)=g(Px) is a tautology. Structural matching –Given structural representation of two functions f and g, there is a structural match if the graphs are isomorphic example

11 Winter 2004ICS 252-Intro to Computer Design Matching algorithms Boolean matching and structural matching: intractable problems Heuristics: –Network covering –Composed of two major pre-processing stages: Decomposition Ensure each vertex is at least one match Partitioning Multiple-output  single-output

12 Winter 2004ICS 252-Intro to Computer Design Covering algorithms Based on structural matching Find common patterns Graphs associated with the library elements are called pattern graphs. Network partitioning into subject graphs Both subject and pattern graphs: DAG and rooted (root?) Structural matching: check isomorphism between subject graphs and pattern graphs

13 Winter 2004ICS 252-Intro to Computer Design Tree-based matching One type operation (degree of vertices shows the type) Tree matching: optimal solution in linear time Simple algorithm that determines if a pattern tree is isomorphic to a subgraph in a tree –Matching root of pattern to a vertex of the subject tree and visiting recursively their children –Isomorphism can be verified by comparing the degrees of pairs of vertices in both trees in top-down fashion until leaves of pattern tree are reached. –If match, the corresponding children are recursively visited. Otherwise, mismatch.

14 Winter 2004ICS 252-Intro to Computer Design Tree based covering Based on dynamic programming Min-area covering Algorithm: –Traverse the tree in a bottom-up fashion –For all vertices of the subject tree, the algorithm determines the matches of locally rooted subtrees with pattern trees. –Three possibilities: If pattern tree and locally rooted subtree are ismorphic, then label the vertex with the cost cell. If pattern tree is ismorphic to a subtree of the locally rooted subject subtree with the same root and a set of leaves L, vertex is labeled with the corresponding cell cost plus the labels of vertices No match

15 Winter 2004ICS 252-Intro to Computer Design Tree-based matching and covering Simple and efficient Pitfalls: –Multiple non-isomorphic patterns for some cells –Some cells such as XOR and XNOR cannot be represented by tree –Structural matching detect a subset of possible matches and don’t permit the don’t care information of library binding

16 Winter 2004ICS 252-Intro to Computer Design Boolean matching Overcome pitfalls of tree-based and structural matching More computationally expensive Better quality solution Based on dynamic programming used in structural matching but more complex

17 Winter 2004ICS 252-Intro to Computer Design Summary Library binding: –key link between logic synthesis and physical design –Based on matching and covering –Structural matching and covering: Intractable problem –Tree based matching and covering : simple and efficient but with some pitfalls –Algorithms : highly dependent on initial decompositions