New Product Introduction: Synchronous SRAM with On-Chip ECC ECC = Error-Correcting Code High-Performance, Low-Power Synchronous SRAMs With On-Chip ECC to Improve Reliability 1,000x

The SRAMs Required by Modern Systems Must Have High Reliability Modern systems need error-free, high-performance Synchronous SRAMs Systems running mission-critical applications need memories with a high RTR1 and zero system errors Data in traditional SRAMs is corrupted by Soft Errors2 caused by background radiation Soft Errors in SRAMs cause functional failures that lead to system downtime Networking Military and Avionics Signal Processing and Computing Today’s systems require error-free, high-performance Synchronous SRAMs with on-chip ECC3 1 Random Transaction Rate: The maximum rate of truly random accesses to memory, expressed in transactions per second (MT/s, GT/s) 2 A data error that results in the state (Logic 1 or Logic 0) of SRAM memory cells being flipped 3 Error-Correcting Code: A method of encoding and decoding a bit stream with extra bits to detect and correct bit errors 3a

Cypress Is the SRAM Market Leader Cypress is a preferred SRAM supplier to all major network equipment providers with: More than 2.7 billion cumulative units shipped 49%1 market share for Synchronous SRAM products Cypress has the broadest Synchronous SRAM portfolio and offers: More than 2,300 Synchronous SRAM products Standard Sync SRAMs and No Bus Latency™ (NoBL™)2 SRAMs with densities from 2Mb to 72Mb Four generations of QDR®3 SRAMs with densities from 18Mb to 144Mb And, now, Synchronous SRAMs with on-chip ECC and 0.01-FIT/Mb4 reliability Cypress is the most dependable Synchronous SRAM supplier with: Lead times of ≤6 weeks with >99% on-time delivery Multiple qualified fabs, assembly sites and test sites Legacy product support for up to 20 years Cypress introduces new Synchronous SRAMs with on-chip ECC that are 1,000x more reliable than standard SRAMs without ECC 1 2014 Gartner and WSTS market research reports estimated for Synchronous SRAM products 2 A Synchronous SRAM that transfers data on the rising edge of the clock signal with either a one (Standard Sync) or zero (NoBL™) clock cycle delay between read and write operations 3 Quad Data Rate: A synchronous SRAM with two ports, each of which transfers data on both the rising and falling edges of a clock signal 4 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data 3b

Terms You Will Hear Today Synchronous SRAM An SRAM device in which read or write operations are synchronized with one or more external clocks Standard Sync SRAM and No Bus Latency™ (NoBL™) A Synchronous SRAM that transfers data on the rising edge of the clock signal with either one (Standard Sync) or zero (NoBL) clock cycle delay between read and write operations Flow-Through and Pipeline Modes Modes of Synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) Soft Error A data error caused by background radiation Soft Error Rate (SER) The rate at which a device is predicted to have Soft Errors Error-Correcting Code (ECC) Data encoded with extra “parity” bits to detect and correct bit errors Failures-in-Time (FIT) per Megabit of Data (FIT/Mb) The projected failure rate of a device One FIT/Mb equals one failure per billion device hours per megabit of data Random Transaction Rate (RTR) The maximum rate of truly random accesses to memory, expressed in transactions per second (MT/s, GT/s) Memories with higher RTR enable proportionally higher processing rates Restriction of Hazardous Substances (RoHS) A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components 4

Design Problems Engineers Face Standard SRAMs without ECC cannot achieve FIT rates of <10 FIT/Mb Today's Synchronous SRAMs have FIT rates of 150-1,500 FIT/Mb Correcting Soft Errors with a system-level ECC solution forces undesirable system design trade-offs System-level error detection and correction increase design complexity and cycle time These solutions require additional memory and error-correction chips, increasing board space and cost Systems require memories with both high performance and low power consumption 10-Gbps to 20-Gbps1 network switches and routers require memory solutions with RTRs of 120 MT/s to 240 MT/s, respectively A 72Mb Standard Sync/NoBL SRAM without ECC that has an RTR of 250 MT/s consumes 1.65 W of active power Cypress Synchronous SRAMs with on-chip ECC solves these problems: Ensures a FIT rate of <0.01 FIT/Mb that is 1,000x lower than a standard SRAM without ECC Offers pin-to-pin compatibility with Cypress’s existing products to simplify design Provides an RTR of 250 MT/s with an active power consumption of 1.05 W Cypress’s Synchronous SRAMs with on-chip ECC provide low-power, error-free memory solutions for systems that require high performance and high reliability 1 Number of data bits transmitted or received at the network interface of a switch or router, expressed in gigabits per second (Gbps) 5

Synchronous SRAM With On-Chip ECC Is a Superior Solution Mitigate risks and reduce the cost of a non-ECC memory based design… By choosing Synchronous SRAM with on-chip ECC as your memory solution… To produce more reliable solutions for critical applications. Synchronous SRAM memory Switches and routers Radar and signal processing Test equipment Automotive Military and aerospace systems r0 r1 r2 r3 r4 r5 r6 d3 d2 d1 en Close after 7 Cycles (SW) Serial Out 1 1.5 Synchronous SRAM with on-chip ECC ECC logic circuitry Additional SRAM memory for ECC 6

Cypress Synchronous SRAMs With On-Chip ECC vs. Competition SRAM Family Features CY7C14xKVE-250x IS61LPSxx-250x GS86xx-250x On-Chip ECC Yes No Soft Error Rate (FIT/Mb) <0.01 >150 5671 RTR (MT/s) 250 Power2 for 72Mb SRAM (mW) 1,056 1,650 1,254 Power2 for 36Mb SRAM (mW) 792 1,485 1,006 Power2 for 18Mb SRAM (mW) 660 957 891 1 GSI Technology application note AN1024 2 Maximum value at 3.3-V core voltage, +85ºC 7

Random Transaction Rate Synchronous SRAM Portfolio (NDA) High Random Transaction Rate (RTR)1 | Low Latency | High Bandwidth Standard Sync and NoBL™ Standard Sync and NoBL™ with ECC2 QDR® -II/ DDR-II QDR-II+/ DDR-II+ QDR-II+X/ DDR-II+X QDR-IV Max RTR1: 250 MT/s Max BW: 18 Gbps Latency: 1 Cycle Pipeline and Flow-through Modes Pipeline and Flow-through Modes Max RTR1: 666 MT/s Max BW: 47.9 Gbps Latency: 1.5 Cycles CIO3 and SIO4 Max BW: 79.2 Gbps Latency: 2 or 2.5 Cycles CIO3and SIO4, ODT5 Max RTR1: 900 MT/s Max BW: 91.1 Gbps Latency: 2.5 Cycles SIO4, ODT5 Max RTR1: 2.1 GT/s Max BW: 153.5 Gbps Latency: 5 or 8 Cycles Dual-Port Bidirectional ODT5 CY7C41xKV13 144Mb; 667-1066 MHz 1.3 V; x18, x36 Burst 2 CY7C147/8xB 72Mb; 133-250 MHz 2.5, 3.3 V; x18, x36 CY7C144/6xA 36Mb; 133-250 MHz 2.5, 3.3 V; x36, x72 CY7C137/8xD 18Mb; 100-250 MHz 3.3 V; x18, x32, x36 CY7C135/6xC 9Mb; 100-250 MHz Auto E7 CY7C134/2xG 2,4Mb; 100-250 MHz CY7C144/6xK CY7C137/8xK CY7C161/2xKV18 144Mb; 250-333 MHz 1.8 V; x9, x18, x36 Burst 2, 4 CY7C141/2xKV18 36Mb; 250-333 MHz 1.8 V; x8, x9, x18, x36 CY7C131/2/9xKV18 18Mb; 250-333 MHz 1.8 V; x8, x18, x36 CY7C1911xKV18 1.8 V; x9 CY7C151/2xKV18 72Mb; 250-333 MHz CY7Cx4/5/6/7xKV18 144Mb; 300-550 MHz 1.8 V; x18, x36 CY7Cx54/5/6/7KV18 72Mb; 250-550 MHz RH6; Burst 2, 4 CY7Cx24/5/6/7xKV18 36Mb; 400-550 MHz CY7Cx14/5/6/7xKV18 18Mb; 400-550 MHz CY7C156/7xXV18 72Mb; 366-633 MHz CY7C126/7x 36Mb; 366-633 MHz CY7C40xKV13 72Mb; 667-1066 MHz CY7C147/8xK 2.5, 3.3 V; x18, x36, x72 Q315 Q116 Q115 NEW NEW NEW NEW Density NEW Random Transaction Rate 1 Rate of truly random accesses to memory, expressed in transactions per second (MT/s, GT/s) 2 Error-Correcting Code 5 On-Die Termination; parts are CY7C2x 3 Common I/O 6 Radiation hardened, military grade 4 Separate I/O 7 AEC-Q100: -40ºC to +125ºC Production Development QQYY Availability Sampling Concept Status 10

Standard Sync SRAM With On-Chip ECC Applications Family Table Switches and routers Radar and signal processing Test equipment Automotive Military and aerospace systems Option Density MPN RTR FIT/Mb3 Standard Sync with On-Chip ECC Pipeline 18 36 72 Mb CY7C1370/2K CY7C1440/2K CY7C1470/2K 250 MT/s <0.01 Standard Sync with On-Chip ECC Flow-Through CY7C1371/3K CY7C1441/3K CY7C1471/3K 133 Features Block Diagram Available in two modes: Pipeline and Flow-Through1 Single-cycle (SCD) and double-cycle (DCD)2 deselect options Bus-width configurations: x18, x36, x72 (72Mb) Two voltage options: 2.5 V and 3.3 V Industrial and commercial temperature grades Error-Correcting Code (ECC) to detect and correct single-bit errors Packages: 165 BGA and 100 TQFP Industry-standard, Restriction of Hazardous Substances (RoHS)-compliant packages Data Port and Control (2.5/3.3V) Input Register ECC Encoder x2 Control Byte Write Address Interface x19-x21 SRAM Array Address Bus Chip Enable Control Logic Clock Test Engine Output Enable JTAG Interface Sync Chip Enable Control Signal x2 Output Enable Clock NoBL x18, x36 Data Port Output Register (Pipeline) ECC Decoder Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Q1 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb) Production: Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb) 1 Modes of Synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 2 Modes of operation in Pipeline mode where the output driver is tri-stated after either a single cycle (SCD) or dual cycle (DCD) of issuing the deselect command 3 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data 11a

NoBL™ SRAM With On-Chip ECC Applications Family Table Switches and routers Radar and signal processing Test equipment Automotive Military and aerospace systems Option Density MPN RTR FIT/Mb2 NoBL™ with On-Chip ECC Pipeline 18 36 72 Mb CY7C1380/2K CY7C1460/2K CY7C1480/2K 250 MT/s <0.01 NoBL™ with On-Chip ECC Flow-Through CY7C1381/3K CY7C1461/3K CY7C1481/3K 133 Features Block Diagram Available in two modes: Pipeline and Flow-Through1 No Bus Latency™ (NoBL) architecture for balanced read and write Bus-width configurations: x18, x36, x72 (72Mb) Two voltage options: 2.5 V and 3.3 V Industrial and commercial temperature grades Error-Correcting Code (ECC) to detect and correct single-bit errors Packages: 165 BGA and 100 TQFP Industry-standard, Restriction of Hazardous Substances (RoHS)-compliant packages Data Port and Control (2.5/3.3V) Input Register ECC Encoder Control x2 Byte Write Address Interface x19-x21 SRAM Array Address Bus Chip Enable NoBL Logic Clock Test Engine Output Enable JTAG Interface NoBL™ Chip Enable Control Signal x2 Output Enable Clock NoBL Chip Enable Data Port x18, x36 Output Register (Pipeline) ECC Decoder Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Q1 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb) Production: Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb) 1 Modes of Synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 2 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data 11b

Here’s How to Get Started Visit the Cypress Synchronous SRAM with ECC web page to learn more Download the Synchronous SRAM Roadmap and Synchronous SRAM with ECC Product Overview Contact Sales to request a preliminary datasheet 12

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36Mb Synchronous SRAM With On-Chip ECC Product Selector Guide Part Number Architecture Option Bus Width Max Freq Voltage Package CY7C1440KVE33-167AXC Standard Sync Pipeline SCD1 x36 167 MHz 3.3 V TQFP CY7C1441KVE33-133AXC Flow-through 133 MHz CY7C1460KVE33-167AXI NoBL Pipeline CY7C1460KVE33-200AXC 200 MHz CY7C1460KVE25-250AXC 250 MHz 2.5 V CY7C1460KVE25-200BZXI BGA CY7C1460KVE25-167AXC CY7C1460KVE33-167BZC CY7C1462KVE33-167AXC x18 CY7C1462KVE25-167BZI Synchronous SRAM with ECC Part Number Decoding CY 7 C 14XX K VEXX XXX XX X X Temperature Range: C = Commercial, I = Industrial Pb Free: X = Pb Free Package Type: BZ = 165-ball BGA, A = 100-pin TQFP Frequency Range: XXX = 100-250 MHz VEXX: VE33 = ECC part with 3.3-V core voltage, VE25 = ECC part with 2.5-V core voltage K = K die revision Part Identifier = 144 x 36M Standard Sync, 146 x 36M NoBL Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress 1 Modes of operation in pipeline mode where output driver is tri-stated after one cycle (SCD) of issuing the deselect command 16

References and Links Cypress Synchronous SRAM webpage: www.cypress.com/sync_SRAMs Synchronous SRAM with ECC web page: www.cypress.com/SyncNoBLECC Contact Sales to request a preliminary datasheet 13. References and Links 18

36Mb SRAM With On-Chip ECC Solution Value $46.20 $16.50 $4.28 $0.01 $4.29 $66.99 Competitor Closest equivalent: GSI GS8320Z36AGT-250V Price: $46.201 BOM Integration Additional SRAM for ECC: 9Mb (GS880Z36CGT-250V) is used to implement ECC scheme to store an additional 6 parity bits per 36 bits of data Value: $16.502 Additional Value Cooling Cost: $7.00 cooling cost/watt x 0.61-W savings GSI solution consumes 1.21 W compared to 0.60 W for Cypress’s solution Value: $4.283 Board Space Savings: GSI GS880Z36CGT-250V Value: $0.014 Competitor Additional SRAM for ECC BOM Integration Value Cooling Cost Board Space Savings Total Additional Value Total Value Delivered Sync SRAM with ECC: Total Cost: 28% Total Savings: CY7C1460KVE25-250AXC $47.965 $19.03 1 Avnet website 500+ units pricing on 09/16/14 2 Avnet website 1ku pricing on 09/16/14 3 Microsoft Data Center costs provided to Schneider Electric 4 0.97-sq-cm space savings at $0.01 per sq cm = $0.01 5 Digikey website 1ku pricing on 09/16/14 19