Enhancing Commodity Scalar Processors with Vector Components for Increased Scientific Productivity

Vectors on Commodity Components Find the minimum set of vector-derived modifications to commodity micros to improve efficiency Deconstructing Vectors (segregate features of vector architecture) –ISA, memory BW, addressing modes, vector regsisters Commodity market has focused on increasing peak flops with SIMD/Vector-like features –High peak flops for little space on silicon, but hard to keep fed with operands –Does not improve efficiency for scientific applications High end (IBM Power series) demonstrates that high memory bandwidth (in bytes/flop) is not an exclusive feature of vectors Efficient utilization of BW requires deep pipelining of memory requests (a natural ability for vectors register loads/stores) –Required by Little’s Law (eg. Power5 requires 3k of requests) –Shift focus from vector ISA (eg. SIMD) to vecregs & addressing modes –Samples include ViVA-2, PERCS programmable cache, and IBM Cell processor

Investigation Collect information on real DOE Scientific codes on Vector architectures –Evaluate where deconstructed features of vector arch. Benefits these codes (and where it fails) –Compare to results on microprocessors (particular interest in new processors that match vector Bytes/flop & Vector systems like X1e with lower bytes/flop than microprocessors) Develop parameterized architectural probes that mimic behavior of full codes –Allows us to run on architectural simulators and test systems to assess impact of new vector-like architectural features on scientific codes Work with vendor partners to develop arch features more suited to improving efficiency of scientific applications –Past work on Tera, ViRAM, IMAGINE, DIVA. –ViVA-2, PERCS, Sun HERO, Impulse –Move towards collaborations with industry to push science-driven advances in processor technology that can also leverage mainstream mass- market components (eg. IBM Power processor customization centers)