A Cross Layer Design Exploration of Charge- Recycled Power-Delivery in Many-Layer 3D-IC Runjie Zhang Kaushik Mazumdar Brett H. Meyer Ke Wang Kevin Skadron Mircea Stan DAC 15’

Outline Introduction Background PDN Modeling for 3D-IC Results and future work

Introduction the number of physical layers in a 3DIC stack is expected to increase in the future, the already serious problems of delivering power to and removing heat from the 3D stack will be even worse. Previous research proposals suggest using the voltage stacking to build the power delivery network for 3D-IC

Voltage Stacking 3D IC power delivery walls arise due to unsustainable increase in current Solution for delivering increased power without increase in current is to increase voltage

Voltage Stacking

SC converter

Switch Capacitor Model

Close loop and Open loop

PDN Modeling for 3D-IC

Simulation Setup Many core Processor Modeling Use 40nm, dual-core ARM Cortex A9 and replicate it 8 times to build a single- layer, 16core processor It can handle the temperature below 100 Celsius with 8 layer of its example 16 core processor

Simulation Setup

Results