1 COMP541 Datapaths II & Control I Montek Singh Mar 22, 2010

Topics  Single cycle MIPS Reading: Chapter 7 Reading: Chapter 7 Verilog code for MIPS at the end (!) Verilog code for MIPS at the end (!) If you don’t feel comfortable with assembly language, pls review Ch. 6 2

First, Top Level of CPU module top(input clk, reset, output [31:0] writedata, dataadr, output [31:0] writedata, dataadr, output memwrite); output memwrite); wire [31:0] pc, instr, readdata; wire [31:0] pc, instr, readdata; // instantiate processor and memories // instantiate processor and memories mips mips(clk, reset, pc, instr, memwrite, dataadr, mips mips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata); writedata, readdata); imem imem(pc[7:2], instr); imem imem(pc[7:2], instr); dmem dmem(clk, memwrite, dataadr, writedata, dmem dmem(clk, memwrite, dataadr, writedata, readdata); readdata);endmodule 3

Top Level Schematic (ISE) 4 MIPS imem dmem

Top Level of MIPS module mips(input clk, reset, output [31:0] pc, output [31:0] pc, input [31:0] instr, input [31:0] instr, output memwrite, output memwrite, output [31:0] aluout, writedata, output [31:0] aluout, writedata, input [31:0] readdata); input [31:0] readdata); wire memtoreg, branch, wire memtoreg, branch, pcsrc, zero, pcsrc, zero, alusrc, regdst, regwrite, jump; alusrc, regdst, regwrite, jump; wire [2:0] alucontrol; wire [2:0] alucontrol; controller c(instr[31:26], instr[5:0], zero, controller c(instr[31:26], instr[5:0], zero, memtoreg, memwrite, pcsrc, memtoreg, memwrite, pcsrc, alusrc, regdst, regwrite, jump, alusrc, regdst, regwrite, jump, alucontrol); alucontrol); datapath dp(clk, reset, memtoreg, pcsrc, datapath dp(clk, reset, memtoreg, pcsrc, alusrc, regdst, regwrite, jump, alusrc, regdst, regwrite, jump, alucontrol, alucontrol, zero, pc, instr, zero, pc, instr, aluout, writedata, readdata); aluout, writedata, readdata);endmodule 5

MIPS Schematic 6

Datapath 7

MIPS State Elements 8 We’ll fill out the datapath and control logic for basic single cycle MIPS First the datapath then the control logic

Let’s Design lw  What does it do? 9

Single-Cycle Datapath: lw fetch  First consider executing lw How does lw work? How does lw work?  STEP 1: Fetch instruction

Single-Cycle Datapath: lw register read  STEP 2: Read source operands from register file

Single-Cycle Datapath: lw immediate  STEP 3: Sign-extend the immediate

Single-Cycle Datapath: lw address  STEP 4: Compute the memory address Note Control

Single-Cycle Datapath: lw memory read  STEP 5: Read data from memory and write it back to register file

Single-Cycle Datapath: lw PC increment  STEP 6: Determine the address of the next instruction

Let’s be Clear  Although the slides said “STEP” … … all that stuff executed in one cycle!!! … all that stuff executed in one cycle!!!  Let’s look at sw  and then R-type 16

Single-Cycle Datapath: sw, write back  Write data in rt to memory

Single-Cycle Datapath: R-type instr  Read from rs and rt  Write ALUResult to register file  Write to rd (instead of rt )

Single-Cycle Datapath: beq  Determine whether values in rs and rt are equal  Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4) BTA = (sign-extended immediate << 2) + (PC+4)

Complete Single-Cycle Processor (w/control)

Control Unit

Review: ALU F 2:0 Function 000A & B 001A | B 010A + B 011not used 100A & ~B 101A | ~B 110A - B 111SLT

Review: ALU Design F 2:0 Function 000A & B 001A | B 010A + B 011not used 100A & ~B 101A | ~B 110A - B 111SLT

Fields: –op: the operation code or opcode (0 for R-type instructions) –funct: the function together, the opcode and function tell the computer what operation to perform Review: R-Type

Controller (2 modules) module controller(input [5:0] op, funct, input zero, input zero, output memtoreg, memwrite, output memtoreg, memwrite, output pcsrc, alusrc, output pcsrc, alusrc, output regdst, regwrite, output regdst, regwrite, output jump, output jump, output [2:0] alucontrol); output [2:0] alucontrol); wire [1:0] aluop; wire [1:0] aluop; wire branch; wire branch; maindec md(op, memtoreg, memwrite, branch, maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, alusrc, regdst, regwrite, jump, aluop); aluop); aludec ad(funct, aluop, alucontrol); aludec ad(funct, aluop, alucontrol); assign pcsrc = branch & zero; assign pcsrc = branch & zero;endmodule 25

Main Decoder module maindec(input [5:0] op, output memtoreg, memwrite, branch, alusrc, output memtoreg, memwrite, branch, alusrc, output regdst, regwrite, jump, output regdst, regwrite, jump, output [1:0] aluop); output [1:0] aluop); reg [8:0] controls; reg [8:0] controls; assign {regwrite, regdst, alusrc, assign {regwrite, regdst, alusrc, branch, memwrite, branch, memwrite, memtoreg, jump, aluop} = controls; memtoreg, jump, aluop} = controls; case(op) case(op) 6'b000000: controls <= 9'b ; //Rtype 6'b000000: controls <= 9'b ; //Rtype 6'b100011: controls <= 9'b ; //LW 6'b100011: controls <= 9'b ; //LW 6'b101011: controls <= 9'b ; //SW 6'b101011: controls <= 9'b ; //SW 6'b000100: controls <= 9'b ; //BEQ 6'b000100: controls <= 9'b ; //BEQ 6'b001000: controls <= 9'b ; //ADDI 6'b001000: controls <= 9'b ; //ADDI 6'b000010: controls <= 9'b ; //J 6'b000010: controls <= 9'b ; //J default: controls <= 9'bxxxxxxxxx; //??? default: controls <= 9'bxxxxxxxxx; //??? endcase endcaseendmodule 26 Why do this?

ALU Decoder module aludec(input [5:0] funct, input [1:0] aluop, input [1:0] aluop, output reg [2:0] alucontrol); output reg [2:0] alucontrol); case(aluop) case(aluop) 2'b00: alucontrol <= 3'b010; // add 2'b00: alucontrol <= 3'b010; // add 2'b01: alucontrol <= 3'b110; // sub 2'b01: alucontrol <= 3'b110; // sub default: case(funct) // RTYPE default: case(funct) // RTYPE 6'b100000: alucontrol <= 3'b010; // ADD 6'b100000: alucontrol <= 3'b010; // ADD 6'b100010: alucontrol <= 3'b110; // SUB 6'b100010: alucontrol <= 3'b110; // SUB 6'b100100: alucontrol <= 3'b000; // AND 6'b100100: alucontrol <= 3'b000; // AND 6'b100101: alucontrol <= 3'b001; // OR 6'b100101: alucontrol <= 3'b001; // OR 6'b101010: alucontrol <= 3'b111; // SLT 6'b101010: alucontrol <= 3'b111; // SLT default: alucontrol <= 3'bxxx; // ??? default: alucontrol <= 3'bxxx; // ??? endcase endcase endmodule 27

Control Unit: ALU Decoder ALUOp 1:0 Meaning 00Add 01Subtract 10Look at Funct 11Not Used ALUOp 1:0 FunctALUControl 2:0 00X010 (Add) X1X110 (Subtract) 1X ( add ) 010 (Add) 1X ( sub ) 110 (Subtract) 1X ( and ) 000 (And) 1X ( or ) 001 (Or) 1X ( slt ) 111 (SLT)

Control Unit: Main Decoder InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 R-type lw sw X101X00 beq X010X01

Single-Cycle Datapath Example: or

Extended Functionality: addi  No change to datapath

Control Unit: addi InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 R-type lw sw X101X00 beq X010X01 addi

Extended Functionality: j

Control Unit: Main Decoder InstructionOp 5:0 RegWriteRegDstAluSrcBranchMemWriteMemtoRegALUOp 1:0 Jump R-type lw sw X101X00 beq X010X01 j XXX0XXX1

Review: Processor Performance Program Execution Time = (# instructions)(cycles/instruction)(seconds/cycle) = # instructions x CPI x TC

Single-Cycle Performance  T C is limited by the critical path (lw)

Single-Cycle Performance Single-cycle critical path: T c = t pcq_PC + t mem + max(t RFread, t sext + t mux ) + t ALU + t mem + t mux + t RFsetup In most implementations, limiting paths are: –memory, ALU, register file. –T c = t pcq_PC + 2t mem + t RFread + t ALU + t RFsetup + t mux

Single-Cycle Performance Example T c = t pcq_PC + 2t mem + t RFread + t mux + t ALU + t RFsetup = [30 + 2(250) ] ps = 925 ps

Single-Cycle Performance Example For a program with 100 billion instructions executing on a single-cycle MIPS processor, Execution Time = # instructions x CPI x T C = (100 × 10 9 )(1)(925 × s) = 92.5 seconds

Any potentials problems?  How do our Block RAMs differ from the RAM illustrated here?  Do we want a Harvard architecture? instruction memory and data memory are separate instruction memory and data memory are separate 40

Next Time  We’ll look at multi-cycle MIPS  Adding functionality to our design 41