Brief Verilog

Building blocks Modules Data types & operators How to code?

Overview Top Module in0 moduleX m P O in1 R T S in2 Wires moduleY my0 out0

Module Creation module alu ( input [3:0] A, input [3:0] B, input [2:0] Control, output reg[3:0] Result, output Zero ); //Code … endmodule

Data Types & Operators

Verilog Modelling Structural Model Behavioral Model Using gates, wires, etc. Behavioral Model Using always blocks, if statements Procedural blocks

Behavioral Example always @ (A or B or Control) case(ALUControl) 3'b000: Result = A & B; // AND 3'b001: Result = A | B; // OR 3'b010: Result = A ^ B; // XOR 3'b101: Result = A + B; // ADD 3'b110: Result = A - B; // SUB 3'b111: Result = (A < B)? 1:0; // SLT - set if less than default: Result = {4{1'b1}}; //undefined ALU operation endcase

Keywords Always @(posedge clk/ negedge clk) Initial If / else Forever Case (cond) endcase Reg Blocking vs non blocking assignment = vs <= Sequential vs Parallel Structural & Behavioral vs Behavioral

Always & If/else example module always_example(); input clk,reset,enable,q_in; output data; always @ (posedge clk) if (reset) begin data <= 0; end else if (enable) data <= q_in; End endmodule

Initial Example initial begin end clk = 0; reset = 0; enable = 0; data = 0; end

Structural Example module addbit (a , // first input b , // Second Input ci , // Carry Input sum , // sum Output co // carry output ); //Input declaration input a; input b; input ci; //Ouput declaration output sum; output co; //Port Data types wire a; wire b; wire ci; wire sum; wire co; //Code starts here assign {co,sum} = a + b + ci; endmodule // End of Module addbit

Keywords assign wire and N-input AND gate nand N-input NAND gate or N-input OR gate nor N-input NOR gate xor N-input XOR gate xnor N-input XNOR gate

Design flow Block Diagram Implementation Simulation FPGA

Basys 2 Board

Example Sw_input Pulse_controller AN 4’b1111 Disp_controller C CLK DP LD rdata1 Reg_file rdata2 raddr1 raddr2 waddr wdata

More… http://web.stanford.edu/class/ee183/handouts_win2003/VerilogQuickRef.pdf Basys board https://www.digilentinc.com/data/products/basys2/basys2_rm.pdf http://www.verilogtutorial.info/