1 Digital Fundamentals Chapter 8 Flip-Flops and Related Devices Resource: CYU / CSIE / Yu-Hua Lee / Not made by Engr. Umar Talha,

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1 Digital Fundamentals Chapter 8 Flip-Flops and Related Devices Resource: CYU / CSIE / Yu-Hua Lee / Not made by Engr. Umar Talha, special thanks to E#ngr. Jahanzeb Ahmed

2 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 3 Figure 8--1 Two versions of SET-RESET (S-R) latches. Open file F08-01 and verify the operation of both latches.

CYU / CSIE / Yu-Hua Lee / E- 4 Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b).

CYU / CSIE / Yu-Hua Lee / E- 5 Figure 8--3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition.

CYU / CSIE / Yu-Hua Lee / E- 6 Figure 8--4 Logic symbols for the S-R and S-R latch.

CYU / CSIE / Yu-Hua Lee / E- 7 Figure 8--5

CYU / CSIE / Yu-Hua Lee / E- 8 Figure 8--6 The S-R latch used to eliminate switch contact bounce.

CYU / CSIE / Yu-Hua Lee / E- 9 Figure 8--7 The 74LS279 quad S-R latch.

CYU / CSIE / Yu-Hua Lee / E- 10 Figure 8--8 A gated S-R latch.

CYU / CSIE / Yu-Hua Lee / E- 11 Figure 8--9

CYU / CSIE / Yu-Hua Lee / E- 12 Figure A gated D latch.

CYU / CSIE / Yu-Hua Lee / E- 13 Figure 8--11

CYU / CSIE / Yu-Hua Lee / E- 14 Figure The 74LS75 quad gated D latches.

CYU / CSIE / Yu-Hua Lee / E- 15 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 16 Figure Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered).

CYU / CSIE / Yu-Hua Lee / E- 17 Figure Operation of a positive edge-triggered S-R flip-flop.

CYU / CSIE / Yu-Hua Lee / E- 18 Figure 8--15

CYU / CSIE / Yu-Hua Lee / E- 19 Figure 8--16

CYU / CSIE / Yu-Hua Lee / E- 20 Figure Edge triggering.

CYU / CSIE / Yu-Hua Lee / E- 21 Figure Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse.

CYU / CSIE / Yu-Hua Lee / E- 22 Figure Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.

CYU / CSIE / Yu-Hua Lee / E- 23 Figure A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.

CYU / CSIE / Yu-Hua Lee / E- 24 Figure 8--21

CYU / CSIE / Yu-Hua Lee / E- 25 Figure A simplified logic diagram for a positive edge-triggered J-K flip-flop.

CYU / CSIE / Yu-Hua Lee / E- 26 Figure Transitions illustrating the toggle operation when J =1 and K = 1.

CYU / CSIE / Yu-Hua Lee / E- 27 Figure 8--24

CYU / CSIE / Yu-Hua Lee / E- 28 Figure 8--25

CYU / CSIE / Yu-Hua Lee / E- 29 Figure Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

CYU / CSIE / Yu-Hua Lee / E- 30 Figure Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.

CYU / CSIE / Yu-Hua Lee / E- 31 Figure Open file F08-28 to verify the operation.

CYU / CSIE / Yu-Hua Lee / E- 32 Figure Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flops.

CYU / CSIE / Yu-Hua Lee / E- 33 Figure Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flops.

CYU / CSIE / Yu-Hua Lee / E- 34 Figure 8--31

CYU / CSIE / Yu-Hua Lee / E- 35 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 36 Figure Basic logic diagram for a master-slave J-K flip-flop.

CYU / CSIE / Yu-Hua Lee / E- 37 Figure Pulse-triggered (master-slave) J-K flip-flop logic symbols.

CYU / CSIE / Yu-Hua Lee / E- 38 Figure 8--34

CYU / CSIE / Yu-Hua Lee / E- 39 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E Flip-Flop Operating Characteristics  Propagation Delay Times t PLH t PHL  Set-up Time t s  Hold Time t h  Maximum Clock Frequency f max  Pulse Widths t w  Power Dissipation

CYU / CSIE / Yu-Hua Lee / E- 41 Figure Propagation delays, clock to output.

CYU / CSIE / Yu-Hua Lee / E- 42 Figure Propagation delays, preset input to output and clear input to output.

CYU / CSIE / Yu-Hua Lee / E- 43 Figure Set-up time (t s ). The logic level must be present on the D input for a time equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry.

CYU / CSIE / Yu-Hua Lee / E- 44 Figure Hold time (t h ). The logic level must remain on the D input for a time equal to or greater than t h after the triggering edge of the clock pulse for reliable data entry.

CYU / CSIE / Yu-Hua Lee / E- 45 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 46 Figure Example of flip-flops used in a basic register for parallel data storage.

CYU / CSIE / Yu-Hua Lee / E- 47 Figure The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.

CYU / CSIE / Yu-Hua Lee / E- 48 Figure Example of two J-K flip-flops used to divide the clock frequency by 4. Q A is one-half and Q B is one-fourth the frequency of CLK.

CYU / CSIE / Yu-Hua Lee / E- 49 Figure 8--42

CYU / CSIE / Yu-Hua Lee / E- 50 Figure 8--43

CYU / CSIE / Yu-Hua Lee / E- 51 Figure Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.

CYU / CSIE / Yu-Hua Lee / E- 52 Figure 8--45

CYU / CSIE / Yu-Hua Lee / E- 53 Figure 8--46

CYU / CSIE / Yu-Hua Lee / E- 54 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 55 Figure A simple one-shot circuit.

CYU / CSIE / Yu-Hua Lee / E- 56 Figure Basic one-shot logic symbols. CX and RX stand for external components.

CYU / CSIE / Yu-Hua Lee / E- 57 Figure Nonretriggerable one-shot action.

CYU / CSIE / Yu-Hua Lee / E- 58 Figure Retriggerable one-shot action.

CYU / CSIE / Yu-Hua Lee / E- 59 Figure Logic symbols for the nonretriggerable one-shot.

CYU / CSIE / Yu-Hua Lee / E- 60 Figure Three ways to set the pulse width of a

CYU / CSIE / Yu-Hua Lee / E- 61 Figure Logic symbol for the 74LS122 retriggerable one-shot.

CYU / CSIE / Yu-Hua Lee / E- 62 Figure 8--54

CYU / CSIE / Yu-Hua Lee / E- 63 Figure A sequential timing circuit using three 74LS122 one-shots.

CYU / CSIE / Yu-Hua Lee / E- 64 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 65 Figure Internal functional diagram of a 555 timer (pin numbers are in parenthesis).

CYU / CSIE / Yu-Hua Lee / E- 66 Figure The 555 timer connected as a one-shot.

CYU / CSIE / Yu-Hua Lee / E- 67 Figure One-shot operation of the 555 timer.

CYU / CSIE / Yu-Hua Lee / E- 68 Figure The 555 timer connected as an astable multivibrator (oscillator).

CYU / CSIE / Yu-Hua Lee / E- 69 Figure Operation of the 555 timer in the astable mode.

CYU / CSIE / Yu-Hua Lee / E- 70 Figure Frequency of oscillation as a function of C 1 and R 1 1 2R 2. The sloped lines are values of R 1 1 2R 2.

CYU / CSIE / Yu-Hua Lee / E- 71 Figure The addition of diode D 1 allows the duty cycle of the output to be adjusted to less than 50 percent by making R 1, R 2.

CYU / CSIE / Yu-Hua Lee / E- 72 Figure Open file F08-63 to verify operation.

CYU / CSIE / Yu-Hua Lee / E- 73 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 74 Figure Two-phase clock generator with ideal waveforms. Open file F08-64 and verify the operation.

CYU / CSIE / Yu-Hua Lee / E- 75 Figure Logic analyzer displays for the circuit in Figure 8-64.

CYU / CSIE / Yu-Hua Lee / E- 76 Figure Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches. Open file F08-66 and verify the operation.

CYU / CSIE / Yu-Hua Lee / E- 77 Chapter 8 Flip-Flops and Related Devices  8-1 Latches  8-2 Edge-Triggered Flip-Flops  8-3 Master-Slave Flip-Flops  8-4 Flip-Flop Operating Characteristics  8-5 Flip-Flop Applications  8-6 One-Shots  8-7 The 555 Timer  8-8 Troubleshooting  8-9 Programmable Logic

CYU / CSIE / Yu-Hua Lee / E- 78 Figure GAL block diagrams.

CYU / CSIE / Yu-Hua Lee / E- 79 Figure The GAL22V10 OLMC.

CYU / CSIE / Yu-Hua Lee / E- 80 Figure The GAL16V8 OLMC.

CYU / CSIE / Yu-Hua Lee / E- 81 Combinational Logic Chapter 8 Digital System Application

CYU / CSIE / Yu-Hua Lee / E- 82 Figure Traffic light control system block diagram.

CYU / CSIE / Yu-Hua Lee / E- 83 Figure Block diagram of the timing circuits.

CYU / CSIE / Yu-Hua Lee / E- 84 Figure 8--72

CYU / CSIE / Yu-Hua Lee / E- 85 Figure 8--73

CYU / CSIE / Yu-Hua Lee / E- 86 Figure 8--74

CYU / CSIE / Yu-Hua Lee / E- 87 Combinational Logic Chapter 8 Problems

CYU / CSIE / Yu-Hua Lee / E- 88 Figure 8--75

CYU / CSIE / Yu-Hua Lee / E- 89 Figure 8--76

CYU / CSIE / Yu-Hua Lee / E- 90 Figure 8--77

CYU / CSIE / Yu-Hua Lee / E- 91 Figure 8--78

CYU / CSIE / Yu-Hua Lee / E- 92 Figure 8--79

CYU / CSIE / Yu-Hua Lee / E- 93 Figure 8--80

CYU / CSIE / Yu-Hua Lee / E- 94 Figure 8--81

CYU / CSIE / Yu-Hua Lee / E- 95 Figure 8--82

CYU / CSIE / Yu-Hua Lee / E- 96 Figure 8--83

CYU / CSIE / Yu-Hua Lee / E- 97 Figure 8--84

CYU / CSIE / Yu-Hua Lee / E- 98 Figure 8--85

CYU / CSIE / Yu-Hua Lee / E- 99 Figure 8--86

CYU / CSIE / Yu-Hua Lee / E- 100 Figure 8--87

CYU / CSIE / Yu-Hua Lee / E- 101 Figure 8--88

CYU / CSIE / Yu-Hua Lee / E- 102 Figure 8--89

CYU / CSIE / Yu-Hua Lee / E- 103 Figure 8--90

CYU / CSIE / Yu-Hua Lee / E- 104 Figure 8--91

CYU / CSIE / Yu-Hua Lee / E- 105 Figure 8--92

CYU / CSIE / Yu-Hua Lee / E- 106 Figure 8--93

CYU / CSIE / Yu-Hua Lee / E- 107 Figure 8--94

CYU / CSIE / Yu-Hua Lee / E- 108 Figure 8--95

CYU / CSIE / Yu-Hua Lee / E- 109 Figure 8--96

CYU / CSIE / Yu-Hua Lee / E- 110 Figure 8--97

CYU / CSIE / Yu-Hua Lee / E- 111 Figure 8--98

CYU / CSIE / Yu-Hua Lee / E- 112 Figure 8--99

CYU / CSIE / Yu-Hua Lee / E- 113 Figure

CYU / CSIE / Yu-Hua Lee / E- 114 Figure

CYU / CSIE / Yu-Hua Lee / E- 115 Figure

CYU / CSIE / Yu-Hua Lee / E- 116 Figure

CYU / CSIE / Yu-Hua Lee / E- 117 Figure

CYU / CSIE / Yu-Hua Lee / E- 118 Figure

CYU / CSIE / Yu-Hua Lee / E- 119 Figure

CYU / CSIE / Yu-Hua Lee / E- 120 Figure

CYU / CSIE / Yu-Hua Lee / E- 121 Figure

CYU / CSIE / Yu-Hua Lee / E- 122 Figure

CYU / CSIE / Yu-Hua Lee / E- 123 Figure

CYU / CSIE / Yu-Hua Lee / E- 124 Figure

CYU / CSIE / Yu-Hua Lee / E- 125 Figure

CYU / CSIE / Yu-Hua Lee / E- 126 Figure

CYU / CSIE / Yu-Hua Lee / E- 127 Figure

CYU / CSIE / Yu-Hua Lee / E- 128 Figure

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