ELEN 468 Lecture 131 ELEN 468 Advanced Logic Design Lecture 13 Synthesis of Combinational Logic II

ELEN 468 Lecture 132 Verilog Code Styles One behavior or functionality can be described with Verilog in different styles Different styled Verilog code may generate different synthesis results Need to understand such difference to design circuit efficiently

ELEN 468 Lecture 133 General Rules for Combinational Logic Avoid to model specific technology Synthesis functionality Ignore timing Avoid feedback loops Feedback loop may result in sequential circuit

ELEN 468 Lecture 134 Combinational Synthesis from Netlist of Primitives Let design be synthesized to remove any redundant logic y = (a+b)(b+c) y = ac + b Example 8.6, page 300

ELEN 468 Lecture 135 Combinational Synthesis from UDPs Any combinational UDP can be synthesized Table entry with “x” is ignored “?” is treated as don’t care Post-synthesis simulation result may be different from pre-synthesis simulation if a table has “x” or “?”

ELEN 468 Lecture 136 Combinational Synthesis from a Cyclic Behavior Combinational logic can be described by a cyclic behavior – enumerate all input cases, otherwise a latch will be inferred A register variable does not necessarily implies storage element Signals appear at RHS of assignment cannot appear on LHS

ELEN 468 Lecture 137 Combinational Synthesis from a Cyclic Behavior: Example module and4_behav( y, x ); input [3:0] x; output y; reg y; integer k; ( x ) begin: check y = 1; for ( k = 0; k <= 3; k = k+1 ) if ( x[k] == 0 ) begin y = 0; disable check; end endmodule module and4_behav( y, x ); input [3:0] x; output y; reg y; integer k; ( x ) begin: check y = 1; for ( k = 0; k <= 3; k = k+1 ) if ( x[k] == 0 ) begin y = 0; disable check; end endmodule x y

ELEN 468 Lecture 138 Combinational Synthesis from Function or Task Functions inherently represent combinational logic Avoid incomplete case statements or incomplete conditionals Task has similar restrictions as a function Avoid timing controls in tasks

ELEN 468 Lecture 139 Constructs to Avoid in Combinational Synthesis – Sequential Behavior Inferred Multiple event controls in same procedural block Named event with edge-sensitive event control Feedback loops PCA with event or delay control Parallel threads: fork … join Suspended activity: wait External disable statement Procedural loops with timing controls Data-dependent loops Tasks with timing controls Sequential UDPs

ELEN 468 Lecture 1310 Simulation Efficiency and PCA module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; (en or a or b or c or d ) y = ~( en & (a | b) & (c | d) ); endmodule module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; (en or a or b or c or d ) y = ~( en & (a | b) & (c | d) ); endmodule module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; ( en ) if ( en ) assign y = ~((a|b) & (c|d)); else assign y = 1; endmodule module orNand1(y, en, a, b, c, d ); input en, a, b, c, d; output y; reg y; ( en ) if ( en ) assign y = ~((a|b) & (c|d)); else assign y = 1; endmodule Less efficient Generally, PCA is efficient on implementing combinational logic in behavioral descriptions Keyword deassign is only used in sequential circuits.

ELEN 468 Lecture 1311 Note Synthesis tool may issue a confusing message about syntax violations because it does not accept your coding style, even though your code is correct in syntax

ELEN 468 Lecture 1312 Unexpected and Unwanted Latch Combinational logic must specify output value for all input values Incomplete case statements and conditionals (if) imply Output should retain value for unspecified input values Unwanted latches

ELEN 468 Lecture 1313 Example of Unwanted Latch module myMux( y, selA, selB, a, b ); input selA, selB, a, b; output y; reg y; ( selA or selB or a or b ) case ( {selA, selB} ) 2’b10: y = a; 2’b01: y = b; endcase endmodule module myMux( y, selA, selB, a, b ); input selA, selB, a, b; output y; reg y; ( selA or selB or a or b ) case ( {selA, selB} ) 2’b10: y = a; 2’b01: y = b; endcase endmodule b a selA’ selB selA selB’ latch y en

ELEN 468 Lecture 1314 Synthesis of case and if case and if statement imply priority Synthesis tool will determine if case items of a case statement are mutually exclusive If so, synthesis will treat them with same priority and synthesize a mux A synthesis tool will treat casex and casez same as case “x” and “z” will be treated as don’t cares Post-synthesis simulation result may be different from pre-synthesis simulation

ELEN 468 Lecture 1315 Example of if and case … input [3:0] data; output [1:0] code; reg [1:0] code; begin // implicit priority if ( data[3] ) code = 3; else if (data[2]) code = 2; else if (data[1]) code = 1; else if (data[0]) code = 0; else code = 2’bx; end … input [3:0] data; output [1:0] code; reg [1:0] code; begin // implicit priority if ( data[3] ) code = 3; else if (data[2]) code = 2; else if (data[1]) code = 1; else if (data[0]) code = 0; else code = 2’bx; end … input [3:0] data; output [1:0] code; reg [1:0] code; case (data) 4’b1000: code = 3; 4’b0100: code = 2; 4’b0010: code = 1; 4’b0001: code = 0; default: code = 2’bx; endcase … input [3:0] data; output [1:0] code; reg [1:0] code; case (data) 4’b1000: code = 3; 4’b0100: code = 2; 4’b0010: code = 1; 4’b0001: code = 0; default: code = 2’bx; endcase … No priority

ELEN 468 Lecture 1316 Technology Mapping Map logic gates to library cells Synthesis tool may map y = a + b into a library adder Synthesis tool will not recognize an adder that is implicitly represented by a hierarchical netlists

ELEN 468 Lecture 1317 Tri-State Buses module stuffToBus1( data, enable, clock ); input enable, clock; output [31:0] data; reg [31:0] outToBus; assign data = ( enable ) ? outToBus : 32’bz; // code to generate outToBus // … endmodule module stuffToBus1( data, enable, clock ); input enable, clock; output [31:0] data; reg [31:0] outToBus; assign data = ( enable ) ? outToBus : 32’bz; // code to generate outToBus // … endmodule Synthesized to a three-state device

ELEN 468 Lecture 1318 Bi-directional Bus Drivers module stuffToBus2 ( data, clock, send_data, rcv_data ); input clock, send_data, rcv_data; inout [31:0] data_to_from_bus; reg [31:0] reg_to_bus; wire [31:0] dataToFrom_bus, inbound_data; assign inbound_data = (rcv_data) ? dataToFrom_bus : 32’bz; assign dataToFrom_bus = (send_data) ? Reg_to_bus : dataToFrom_bus; endmodule module stuffToBus2 ( data, clock, send_data, rcv_data ); input clock, send_data, rcv_data; inout [31:0] data_to_from_bus; reg [31:0] reg_to_bus; wire [31:0] dataToFrom_bus, inbound_data; assign inbound_data = (rcv_data) ? dataToFrom_bus : 32’bz; assign dataToFrom_bus = (send_data) ? Reg_to_bus : dataToFrom_bus; endmodule Core Circuit 32 inbound_data reg_to_bus dataToFrom_bus send_data rcv_data

ELEN 468 Lecture 1319 Exercise 4

ELEN 468 Lecture 1320 Simulation Output `timescale 1ns/100ps module m(y,x); output y, input x; not #1.234 (y,x); endmodule `timescale 10ns/100ps module modA; wire a; reg b; m m1(b, a); initial $monitor ( $time, “ realtime=%f, a=%b, b=%b”, $readtime, a, b); initial begin #10 a = 0; #10 a = 1; #10 $finish; end endmodule `timescale 1ns/100ps module m(y,x); output y, input x; not #1.234 (y,x); endmodule `timescale 10ns/100ps module modA; wire a; reg b; m m1(b, a); initial $monitor ( $time, “ realtime=%f, a=%b, b=%b”, $readtime, a, b); initial begin #10 a = 0; #10 a = 1; #10 $finish; end endmodule 0 realtime=0.0 a=x b=x 10 realtime=10.0 a=0 b=x 10 realtime=10.12 a=0 b=1 20 realtime=20.0 a=1 b=1 20 realtime=20.12 a=1 b=0 0 realtime=0.0 a=x b=x 10 realtime=10.0 a=0 b=x 10 realtime=10.12 a=0 b=1 20 realtime=20.0 a=1 b=1 20 realtime=20.12 a=1 b=0

ELEN 468 Lecture 1321 Transistor Level Structural Code module nand2( y, a, b ); output y; input a, b; supply1 pwr; pulldown ( y ); pmos( y, pwr, a ); pmos( y, pwr, b ); endmodule module nand2( y, a, b ); output y; input a, b; supply1 pwr; pulldown ( y ); pmos( y, pwr, a ); pmos( y, pwr, b ); endmodule Y V dd A B