Group M1 - Enigma Machine Design Manager: Prateek Goenka Adithya Attawar (M1-1) Shilpi Chakrabarti (M1-2) Zavo Gabriel (M1-3) Mike Sokolsky (M1-4) Milestone #4 - 2/6/06 Gate Level Design

Status Update Completed: Completed: Design ChosenDesign Chosen Initial ArchitectureInitial Architecture Behavioral Verilog and C SimulationBehavioral Verilog and C Simulation Floorplan, Size Estimation, Transistor CountFloorplan, Size Estimation, Transistor Count Gate-Level Verilog DesignGate-Level Verilog Design Behavioral Verilog of new moduleBehavioral Verilog of new module In Progress In Progress Schematic Verilog DesignSchematic Verilog Design Gate level Verilog for new moduleGate level Verilog for new module To Do: To Do: LayoutLayout DRC/LVSDRC/LVS TestingTesting

Design Decisions Wheel logic modified Wheel logic modified 2 sets of ROM for each wheel2 sets of ROM for each wheel Implementation of new module Implementation of new module Modernizing the Enigma MachineModernizing the Enigma Machine Add an asymmetric key encryption to transmit the wheel positions and Stecker Board positionsAdd an asymmetric key encryption to transmit the wheel positions and Stecker Board positions Using Prime numbers that will be calculated off chipUsing Prime numbers that will be calculated off chip

Asymmetric Key Encryption The Encryption is based on a public- private key combination The Encryption is based on a public- private key combination Public Key pair (e,N)Public Key pair (e,N) Private Key pair (d,N)Private Key pair (d,N) N is a large number that is a product of 2 primesN is a large number that is a product of 2 primes Code = message^d mod(N)Code = message^d mod(N) Message = Code^e mod(N)Message = Code^e mod(N)

Behavioral Verilog module rsa(ciphertxt, plaintxt, exponent, modulus, clk); output [15:0] ciphertxt; input [4:0] plaintxt; input [11:0] exponent; input [11:0] modulus; input clk; reg [4:0] plainreg; reg [16:0] datareg; reg [11:0] outreg; integer i; assign ciphertxt = outreg; initial i = 0; clk) begin if( i == 0 ) begin plainreg = plaintxt; datareg = plainreg; i = i+1; end else if( i < exponent ) begin datareg = (datareg * plainreg) % modulus; i = i+1; end else begin outreg = datareg; i = 0; end end endmodule output [15:0] ciphertxt; input [4:0] plaintxt; input [11:0] exponent; input [11:0] modulus; input clk; reg [4:0] plainreg; reg [16:0] datareg; reg [11:0] outreg; integer i; assign ciphertxt = outreg; initial i = 0; clk) begin if( i == 0 ) begin plainreg = plaintxt; datareg = plainreg; i = i+1; end else if( i < exponent ) begin datareg = (datareg * plainreg) % modulus; i = i+1; end else begin outreg = datareg; i = 0; end end endmodule

Clocking Issues Design requires complex control over clock signals to different modules. Design requires complex control over clock signals to different modules. Different modules need different clocksDifferent modules need different clocks Also depends on state, for instance:Also depends on state, for instance: Wheel module, during Set phase, is clocked at the global clock rate, however during character operations it is clocked only once per encode cycle. Wheel module, during Set phase, is clocked at the global clock rate, however during character operations it is clocked only once per encode cycle. FSM includes clock modulators for various components that run at different speeds.FSM includes clock modulators for various components that run at different speeds.

Updated Transistor Count Transistor Count: Transistor Count: Muxes = 550Muxes = 550 RAM = 1150RAM = 1150 ROM = 4700ROM = 4700 Adders/Dividers = 450Adders/Dividers = 450 Registers = 800Registers = 800 Counters = 1250Counters = 1250 FSM = 300FSM = 300 Total: 9200 Total: 9200

Block Sizes (estimates) Adder % 26: 3500 um^2 Adder % 26: 3500 um^2 RAM: um^2 RAM: um^2 ROM:30000 um^2 ROM:30000 um^2 Counters:6000 um^2 Counters:6000 um^2 Control/FSM:3000 um^2 Control/FSM:3000 um^2 Registers:2500 um^2 Registers:2500 um^2 Total: 55,000 um^2 Total: 55,000 um^2

Floor Plan Counter & Wheel Reg. FSM & Data Reg. RAM 5-bit Adder + 5-bit %26 ROM

Metal Layers Standard Usage: Standard Usage: Metal 1Metal 1 Gate connections, V++, Gnd Gate connections, V++, Gnd Metal 2Metal 2 Inter-gate connections, local routing Inter-gate connections, local routing Metal 3Metal 3 Global routing, horizontal Global routing, horizontal Metal 4Metal 4

Main Verilog Module // Main module module enigma (charout, charin, usestek, stekset, numwheels, wheelord, wheelpos, reset, set, clk); output [4:0] charout; input [4:0] charin, input [4:0] stekset, wheelset; input [2:0] wheelord; input usestek, reset, set, clk; wire [4:0] mux0out, mux1out, mux2out, mux3out, mux4out, mux5out, cregout, nregout; wire [4:0] add0out, add1out, ram0out, rom0out, rom1out, wheelpos; wire [2:0] wheel; register5b creg( cregout, mux0out, clk); register5b nreg( nregout, mux1out, clk); register5b oreg( charout, mux2out, clk); adder5bmod26 add0( add0out, nregout, cregout); adder5bmod26 add1( add1out, 5'b01101, add0out); countunit wheels( curwheel, curwheelpos, wheelset, wheelnum, wheelpos, wheelord, reset, set, clk); fsm fsm0( mux0sel, mux1sel, mux2sel, mux3sel, mux4sel, loadcnt, ramrw, ramclk, reset, set,clk); rom234x5b rom0( rom0out, {curwheel, mux3out}); rom26x5b rom1( rom1out, cregout); ram26x5b ram0( ram0out, ramrw, mux4out, stekset, ramclk); mux5bx2 mux0( mux0out, mux0sel, charin, mux2out); mux5bx2 mux1( mux1out, mux1sel, rom0out, curwheelpos); mux5bx4 mux2( mux2out, mux2sel, ram1out, rom1out, cregout, add0out); mux5bx2 mux3( mux3out, mux3sel, add0out, add1out); mux5bx2 mux4( mux4out, mux4sel, cregout, loadcnt); endmodule

Obviously this is too small!!!

Problems & Questions Design is too small Design is too small Planning Additional ModulesPlanning Additional Modules “Random” wheel motion based on state of machine “Random” wheel motion based on state of machine Changing steckerboard parings. Changing steckerboard parings. Grouping characters (block cypher) Grouping characters (block cypher) Have the previous character(s) influence encoding/decoding *** Have the previous character(s) influence encoding/decoding *** Public/Private Key Generation (Unmatched encryption/decryption) ****** Public/Private Key Generation (Unmatched encryption/decryption) ****** Increase data-path(8,12,16-bit operations?)Increase data-path(8,12,16-bit operations?)