Technion - Israel institute of technology department of Electrical Engineering High speed digital systems laboratory 40Gbit Signal Generator for Ethernet Characterization presentation Developers : Ben-Elazar Doron and Atila Fuad Mentor : Dr. Bar-On David Nov 16, 2010

40Gbit SG Agenda  Background  Project Objectives  System Block Diagram  FPGA Block Diagram  Technical Specifications  Risks  Gantt Chart

40Gbit SG Background Debugging a modern communication chip requires the ability to generate high speed L1 & L2 Ethernet signals on all ports of the chip. High speed Ethernet signals (41.25 GHz) can be generated by commercial tools, e.g. IXIA, however they are expensive and deal mainly with higher software layers.

40Gbit SG Project Objectives The Target is to generate 40Gbps Ethernet channel Split into two semesters: Project A – Winter Sem. 2010/11: 10Gbps Traffic. generate hard coded patterns. Project B – Spring Sem. 2011: Continuation of Project A. Generating 40Gbps Traffic. GUI Software for Frame Stream Definition.

40Gbit SG System Block Diagram 10Gbps Signal Generator

40Gbit SG System Block Diagram Final 40Gps Signal Generator

40Gbit SG FPGA Block Diagram

40Gbit SG Technical Specifications Software Tools: Quartus Design Tool Altera USB Programming Tool The Mega Core Functions (PHY+PCS+PMA) Hardware: Altera Stratix IV with 10Gbps Ser-Des Board with SFP+ Modules 10Gbps Link Partner – IXIA PC Fiber Optic Cable Hardware Programming Language: VERILOG Output: Valid Ethernet Packets Transmitted by 64b/66b coding protocol

40Gbit SG Risks Board not arriving on time – We ordered the board 2 months ahead. Defective modules – Ordering two boards. Knowledge gap – Mini project with Altera.

40Gbit SG Gantt Chart

40Gbit SG Gantt Chart – In Depth