Tools for Discovery Digital Pulse Processing for Physics Applications Ganil 2 February 2011 Carlo Tintori

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Outline Description of the hardware of the waveform digitizers Overview on the CAEN Digitizer family Use of the digitizers for physics applications Comparison between the traditional analog acquisition chains and the new fully digital approach DPP algorithms: Pulse triggering Zero suppression Pulse Height Analysis Charge Integration Gamma-Neutron discrimination Time measurement Multi Channel Scaler

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited The principle of operation of a waveform digitizer is the same as the digital oscilloscope: when the trigger occurs, a certain number of samples is saved into one memory buffer (acquisition window) However, there are important differences: –no dead-time between triggers (Multi Event Memory) –multi-board synchronization for system scalability –high bandwidth data readout links –on-line data processing (FPGA or DSP) Digitizers vs Oscilloscopes

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Highlights VME, NIM, PCI Express and Desktop VME64X, Optical Link (CONET), USB 2.0, PCI Express Interfaces available Memory buffer: up to 10MB/ch (max events) Multi-board synchronization and trigger distribution Programmable PLL for clock synthesis Programmable digital I/Os Analog output with majority or linear sum FPGA firmware for Digital Pulse Processing Software for Windows and Linux

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Digitizers Table

Architecture Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited

Traditionally, the acquisition chains for radiation detectors are made out of mainly analog circuits; the A to D conversion is performed at the very end of the chain Nowadays, the availability of very fast and high precision flash ADCs permits to design acquisition systems in which the A to D conversion occurs as close as possible to the detector The data throughput is extremely high: it is no possible to transfer row data to the computers and make the analysis off- line! On-line digital data processing in needed to extract only the information of interest (Zero Suppression & Digital Pulse Processing) The aim of the DPP for Physics Applications is to provide FPGA algorithms able to make in digital the same functions of analog modules such as Shaping Amplifiers, Discriminators, Charge ADCs, Peak Sensing ADCs, TDCs, Scalers, Coincidence Units, etc. Digitizers for Physics Applications

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Traditional chain: example 1 charge sensitive preamplifiers

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited The QDC is not self-triggering; need a gate generator need delay lines to compensate the delay of the gate logic Traditional chain: example 2 trans-impedance (current sensitive) preamplifier

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited One single board can do the job of several analog modules Full information preserved Reduction in size, cabling, power consumption and cost per channel High reliability and reproducibility Flexibility (different digital algorithms can be designed and loaded at any time into the same hardware) Benefits of the digital approach

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Standard Firmware: common trigger on all channels simultaneously programmable record length and pre/post trigger channels self trigger: digital discriminator with programmable threshold multi board synchronization (clock, sync and trigger distribution) trigger time stamps multi event memory buffers (up to 1024 events) waveform mode only (raw data) DPP Firmware trigger and timing filters for pulse identification and triggering channels can trigger independently energy filters for the pulse height analysis (trapezoidal filters) energy filters for the digital charge integration (digital QDC) configurable event data format (time and/or energy and/or waveform) individual trigger propagation on channel basis, also from board to board pulse shape analysis (e.g. gamma neutron discrimination) event data packing for high counting rate Standard vs DPP firmware

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Raw waveform mode vs DPP events

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Individual vs Common trigger CommonIndividual 400 ns = samples = 300 bytes/event (2ch) 80 ns = 20 samples = 30 bytes/event empty event

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Trigger and timing filter (I) Pulse triggering is the basis for all DPP and Zero Suppression algorithms Fast Shaping filter: RC-CR N (N=1, 2) Immune to baseline fluctuation and low frequency noise (ground loop) Pulse identification also with the presence of pile-up High frequency noise rejection (RC like mean filter) Can operate as a digital CFD Zero crossing for precise timing information Off-line interpolation to overcome the sampling period granularity Zero crossing of CFD can also be used for rise time discrimination

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Trigger and timing filter (II)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Zero Suppression Data reduction algorithms can be developed to reduce the data throughput: – Full event suppression: one event (acquisition window) is discarded if no pulse is detected inside the window – Zero Length Encoding: only the parts exceeding the threshold (plus a certain number of samples before and after) are saved.

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP for the Pulse Height Analysis (DPP-TF) Digital implementation of the shaping amplifier + peak sensing ADC (Multi-Channel Analyzer) Charge sensitive preamplifier directly connected to the digitizer Implemented in the 14 bit, 100MSps digitizers (mod. 724) Use of trapezoidal filters to shape the long tail exponential pulses Pile-up rejection, Baseline restoration, ballistic deficit correction High counting rate, very low dead time Energy and timing information can be combined Best suited for high resolution spectroscopy (HPGe and Si detectors)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-TF Block Diagram

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Example of trapezoidal filter output Pile-up Trapezoid Height = Energy

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-TF / Analog Chain set-ups N1470 High Voltage N968 Shaping Amplifier N957 Peak Sensing ADC DT MSps Digitizer + DPP-TF Energy Time Ge / Si C.S. PRE

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited High Rate spectroscopy (DPP-TF) Rise Time Discriminator (RTD) Detection of pulses piling-up on the rising edge Cancellation of the sum peaks Pulse count rate correction (true rate) Baseline Restorer Programmable number of points for the BL calculation Programmable hold-off for a better BL recovery Constraints on the pulse separation

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-TF: Test Results with CdTe 70 KHz200 KHz Sum Peaks with and withou RTD 800 KHz

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Dead Time (DPP-TF) Dead-timeless acquisition (no conversion time) Double pulse resolution  Rise Time (two pulses separated by at least the rise time can be distinguished) The rise time discriminator allows double pulses piling up on the rising edge to be detected and counted twice Although pile-up causes the loss of some energies, the DPP-TF is able to get the timestamps of nearly all pulses: true rate can be calculated Residual multiple pulses that cannot be distinguished (despite the RTD) can be taken into account on a statistical basis Histogram (spectrum) calculated off-line: easy implementation of techniques for the ‘dead-time’ correction (loss of energy counts) The number and the position of lost counts is known: they can be dynamically re-distributed on the histogram. This is very important in the cases where the activity is not constant in time.

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Individual inter-channel triggering (DPP-TF) Mainly needed in segmented (cloves) detectors One channel triggers itself and also neighbour channels Individual TRG-IN and TRG-OUT lines from each channel to the Front Panel GPIO connector (8 inputs + 8 outputs) External trigger unit (V1495) for the coincidence matrix implementation Can work also between cards Available in the new DPP-TF (724 series) Can be implemented in the 720 and 751 series as well

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Pulse Shape Analysis (DPP-TF) Some applications need to perform pulse shape analysis to validate or correct the energy/timestamp information Usually a small set of samples (short waveform) is required; for the DPP-TF, this is typically the rising edge Unlike the ‘oscilloscope like’ acquisition mode, the recording of this waveform chunk has a little overhead in the readout rate Also used to improve the timestamp resolution: just two samples around the CFD zero crossing linearly interpolated off-line permit to make the resolution up to 100 times better than sampling period

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-TF: Test Results 1.33 MeV: 1.98 KeV Germanium Detectors at LNL (Legnaro - Italy) in Nov-08 and Feb-09, at GSI (Germany) on May-09, at INFN-MI on Jan-10, in Japan on Feb-10, at Duke University (USA) on Jul- 10; Palermo on Jan 2011; resolution = MeV ( 60 Co ) Silicon Strip (SSSSD and DSSSD) and CsI detectors in Sweden at Lund and Uppsala (ion beam test) CdTe at high rate (up to 800KHz) for spectroscopy imaging NaI detectors in CAEN (see demo) PET in U.S.A. Homeland security application using CsI BGO detector at ENEA ‘Centro Ricerche Casaccia’ (Rome) 228 Th with DSSSD 60 Co with Ge

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP for the Charge Integration (DPP_CI) Digital implementation of the QDC + discriminator and gate generator Implemented in the 12 bit, high speed digitizers ( Mod. 720 (*) ) Self-gating integration; no delay line to fit the pulse within the gate Baseline restoration (pedestal cancellation) Extremely high dynamic range Dead-timeless acquisition (no conversion time) Energy and timing information can be combined Coincidences can be easily applied off-line Typically used for PMT or SiPM/MPPC readout (*) Implementation in the Mod751 is a work in progress

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-CI Block Diagram

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-CI / Analog Chain set-ups N1470 High Voltage DT MSps Digitizer + DPP-CI Charge Time NaI(Tl) PMT Dual Timer N93B Delay N108A QDC V792N CFD N842 TDC V1190 Time Splitter A315

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-CI: Test Results DPP-CIAnalog QDC Energy (MeV)Res (%) ( 137 Cs Compton edge) 9.41   ( 137 Cs Photopeak) 7.01   ( 60 Co Photopeak) 5.67   ( 60 Co Photopeak) 5.46   ( 60 Co Sum peak) 3.82   0.24 Resolution = FWHM * 100 / Mean NaI detector and PMT directly connected to the QDC or digitizer

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-CI: Other Tests Tested with SiPM/MPPC detectors at Univerità dell’Insubria (Como – Italy) and in CAEN (2009/2010): – Dark Counting Rate – LED pulser – Readout of a 3x3mm Lyso Crystal + Gamma source – Readout of a scintillator tile for beta particles 0.5 ph 1.5 ph 2.5 ph Threshold scan

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP for  -n Discrimination Digital implementation of the  E/E or Rise Time discriminator (both are Pulse Shape Analysis) Digital  E/E: double gate charge integration (same as DPP-CI but with two gates); applied to fast detectors (typ. organic liquid scintillators) Digital Rise Time discrimination:  T in the Zero Crossing of two CFDs at 25% and 75%; applied to integrated output (either from C.S. preamp or digital integrator) PSA used to discard unwanted events (typ. gammas); good events saved including waveform, energy and time stamp Dead-timeless acquisition (no conversion time) Algorithms tested at Duke University on July 2010 (off-line). FPGA implementation just finished. Will be tested next week.

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP-NG vs DPP-CI Dual Gate Gate position and length settings with 4 ns granularity (DPP-CI has 8 ns) Gate position can be referred to either the threshold crossing or the pulse peak PSD parameter Q SHORT / (Q LONG -Q SHORT ) can be used to decide whether an event has to be saved or discarded Better baseline restoration Improved readout (event packing) Two Channel coincidence discontinued Need big FPGA option!

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited  -n Discrimination Block Diagram (I) Algorithms tested off-line Firmware under test

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited  -n Discrimination Block Diagram (II) Algorithms tested off-line Firmware not planned

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited  -n Discrimination: preliminary results (I)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited  -n Discrimination: preliminary results (II)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited  -n Discrimination: preliminary results (III)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited  -n Discrimination: preliminary results (IV)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP for Time Measurements Digital implementation of the TDC + CFD DPP-TF and DPP-CI give time stamps with the resolution of the sampling period (10 ns and 4 ns,  = Ts/  12); interpolation can improve timing resolution Extremely high dynamic range Dead-timeless acquisition (no conversion time); can manage long bursts of pulses (theoretical unlimited double pulse resolution) Big dependence of the resolution from the rise-time and amplitude of the pulses (  V/  T)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Digital CFD and Timing Filters NOTE: the higher ZC slope and the lower tail, the better filter

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited ZC timing errors The timing resolution is affected by three main sources of noise: –Electronic noise in the analog signal (not considered here) –Quantization error Eq –Interpolation error Ei Both simulations and experimental test demonstrate that there are two different regions: When Rise Time > 5*Ts the pulse edge can be well approximated to a straight line, hence Ei is negligible. The resolution is proportional to the rise time and to the number of bits of the ADC. When Rise Time < 5*Ts the approximation to a straight line is too rough and Ei is the dominant source of error. The resolution is still proportional to the number of bit but becomes inversely proportional to the rise time. Resolution improvement expected for cubic interpolation. The best resolution is for Rise Time = 5*Ts, regardless the type of digitizer The resolution is always proportional to the pulse amplitude (more precisely to the slope  V/  T)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Sampling Clock phase effect (RT<5Ts) (I) DELAY AB = N * Ts: same clock phase for A and B  same interpolation error  ERR A  ERR B  Error cancellation in calculating TIME AB TIME AB = (ZC A + ERR A ) – (ZC B + ERR B ) = ZC A – ZC B + (ERR A - ERR B ) DELAY AB = (N+0.5) * Ts: rotated clock phase for A and B  different interpolation error  ERR A  ERR B  No error cancellation. ERR A and ERR B are symmetric: twin peak distribution When rise time < 5*Ts, the interpolation error has a big variation with the phase between the rising edge and the sampling clock.

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Sampling Clock phase effect (RT<5Ts) (II) DELAY = N * Ts DELAY = (N + 0.5) * Ts

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Sampling Clock phase effect (RT<5Ts) (III) 10bit – 1GSps 12bit – 250MSps 14bit – 100MSps Vpp = 100mV Rise Time = Ts Emulation

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Sampling Clock phase effect (RT<5Ts) (IV) Vpp = 100mV Mod720: 12bit 250MSps Emulation 5 ns 10 ns 15 ns 20 ns 30 ns Rise Time

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Preliminary results: Mod724 DELAY AB = (N+0.5) * Ts (worst case) 50 mV 100 mV 200 mV 500 mV (14 bit, 100 MS/s) RiseTime (ns) StdDev (ns)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Preliminary results: Mod720 50mV 100mV 200mV 500mV (12 bit, 250 MS/s) DELAY AB = (N+0.5) * Ts (worst case) RiseTime (ns) StdDev (ns)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Preliminary results: Mod751 50mV 100mV 200mV 500mV (10 bit, 1 GS/s) DELAY AB = (N+0.5) * Ts (worst case) NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot RiseTime (ns) StdDev (ns)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Mod724 vs Mod720 vs Mod bit, 1 GS/s 12 bit, 250 MS/s 14 bit, 100 MS/s RiseTime (ns) StdDev (ns) Amplitude = 100 mV

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited 2 GS/s StdDev (ns) Amplitude (mV)   2 ps ! RT = 1 ns - worst case RT = 1 ns - best case RT = 5 ns The cubic interpolation can reduce the gap between best and worst case as well as increase the resolution for small signals!

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited DPP for Pulse Counting (SCA) Digital implementation of the discriminator + scaler (Single-Channel Analyzer) Can be implemented in the high density digitizers (mod. 740) Pulse Triggering: baseline restoration, noise rejection, etc… Single or Multi-Channel Energy Windowing