Update on the Design Implementation Methodology for the 130nm process Microelecronics User Group meeting TWEPP 2010 – Aachen Sandro Bonacini CERN PH/ESE

Sandro Bonacini - PH/ESE - Motivation Mixed Signal Design flow methodology  Open Access based Implementation of Digital-On-Top ASICs  Script based flow Using the IBM 130 nm standard cell library

Sandro Bonacini - PH/ESE - Design flow components Tools  Virtuoso (OA based)  SOC Encounter 8.1 (velocity)  Conformal 8.1  EXT (QRC)  Assura 3.2  Calibre Design Kits  IBM CMOS8RF DM design kit V1.7 3 thin, 2 thick, 3 RF metals.  IBM CMOS8RF LM design kit V1.7 6 thin, 2 thick metals.

Sandro Bonacini - PH/ESE - Enhancements Digital library  I/O pads Implement missing Cadence/Virtuoso views  Functional and symbol views for simulation Fixed existing views  Pin mismatches of power pads  Abstract power pin width  Layout fixes New corner cells with 45 degrees bend  Standard cells New filler cells conforming to PC & RX pattern density rules New double vias for denser routing / better yield

Sandro Bonacini - PH/ESE - Enhancements Implementation flow  Added support for multiple power domains Analog, digital, …  Support for P&R of mixed signal ASICs and third-party IP blocks  Better integration between Virtuoso and Encounter Automatic final netlist import into Virtuoso  Automated physical verification DRC and LVS  Other fixes Scan chain reordering Antenna rule definition for Encounter Two-steps routing for DM metal stack to avoid antenna violations  1 st pass on 3 metals (only thin)  2 nd pass on 5 metals (thin+thick)

“Digital on Top” Design Flow 30/3/10 6 SOC_Encounter Chip Design SOC_Encounter Chip Design Virtuoso Analog Block Creation Virtuoso Analog Block Creation

Mixed-signal example design  Analog IP block: DAC  Digital IP block: SRAM  Digital block: I2C slave Synthesizable RTL code Triple Module Redundancy  Two separate power supplies Analog, digital 30/3/10 7 A realistic example of a Mixed Signal ASIC to demonstrate the design flow:

Sandro Bonacini - PH/ESE - Synthesis: RTL Compiler [rc] Timing constraints:  Clock definitions  Input delays, fanout, transition, etc.  Output load, etc.

Sandro Bonacini - PH/ESE - Design import: Encounter Reference design used in the AMS workshop:  I2C slave connected to SRAM DAC (with separate analog power supply) registers DAC SRAM

Sandro Bonacini - PH/ESE - Floorplanning & power routing Define  Chip/core size  target area utilization  I/O placement  module placement in case of TMR or other special constraints Power planning/routing  Core/block rings and stripes DACSRAM

Power/ground connections Placement Tap cells Standard cells Scan-chain reordering

Multiple power domains Analog & digital blocks  Separate power supplies.  Insertion of Power Breaker peripheral pads. DAC SRAM

Sandro Bonacini - PH/ESE - Clock tree synthesis & signal routing Clock tree synthesis Routing on thin metals Routing on all metals

Sandro Bonacini - PH/ESE - DFM: Antenna fix Re-routes long nets Inserts tie-down diodes

Sandro Bonacini - PH/ESE - Via optimization

Sandro Bonacini - PH/ESE - Cells & metal fill

Sandro Bonacini - PH/ESE - Back to Virtuoso ! ASIC design is present in Virtuoso.  Scripts take care of changing abstracts into real layouts  Automatic import of netlist DAC SRAM

Calibre DRC – Assura LVS

Sandro Bonacini - PH/ESE - Thank you… Implementation of digital-on-top mixed signal ASICs  Using the IBM 130 nm standard cell library  Defined methodology compatible with mixed signal design flows  Presented in the AMS courses Future plans  Add signal integrity checks Celtic  Automate additional DRC checks (ortho/grid, …)