IT-SOC 2002 © 스마트 모빌 컴퓨 팅 Lab 1 RECONFIGURABLE PLATFORM DESIGN FOR WIRELESS PROTOCOL PROCESSORS

2 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab ABSTRACT Low-energy protocol processing is a crucial issue in next generation wireless systems. In modern wireless system design, this problem is tightly coupled with the signal processing needs. Fierce market competition and inventive wireless applications are imposing stricter design requirements in energy consumption, cost, size and flexibility. To deal with these unique constraints, we incorporate the platform-based design methodology to deal with these constraints by advocating reusability. This paper presents this methodology, and its application on PicoRadio, a cutting-edge wireless system. In particular, we describe the design of a reconfigurable architecture optimized for protocol processing.

IT-SOC 2002 © 스마트 모빌 컴퓨 팅 Lab 3 TABLE OF CONTENTS 1.INTRODUCTION 2.PLATFORM-BASED DESIGN 3.FUNCTIONAL KERNELS OF WIRELESS PORTOCOL STACKS 4.RECONFIGURABLE ARCHITECTURE 5.CONCLUSION

4 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab 1. INTRODUCTION Modern Design Challenges Modern Design Challenges Problems Problems Need for low-cost, small-size Need for low-cost, small-size Need for low-energy, high-throughput protocol processing Need for low-energy, high-throughput protocol processing Need for high-speed in internet Need for high-speed in internet Need for a shorter design time and greater design complexity Need for a shorter design time and greater design complexity Solutions Solutions Research of standard in protocol processing Research of standard in protocol processing Finding a new design methodologies  the design of a low-power reconfigurable architecture for processing the lower layers of PicoRadio protocol stack Finding a new design methodologies  the design of a low-power reconfigurable architecture for processing the lower layers of PicoRadio protocol stack

5 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab 2. PLATFORM-BASED DESIGN Concept of platform-based design Concept of platform-based design purposes purposes Solution of shorter design time and greater design complexity Solution of shorter design time and greater design complexity Satisfaction for low-energy, high-throughput protocol processing and high- speed in internet Satisfaction for low-energy, high-throughput protocol processing and high- speed in internet Structure Structure It consist of three-phase design methodology It consist of three-phase design methodology –The first step : The identification of a system platform Kernel Extraction via Functional Profiling Kernel Extraction via Functional Profiling Reconfigurable Fabric Exploration Reconfigurable Fabric Exploration –The second step : Platform instantiation Configurable Platform Configurable Platform Functional specification Functional specification Mapping Mapping Performance Evaluation Performance Evaluation –The final step : implementation of the system Implementation Implementation

6 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Figure 1: Three-phase design methodology

7 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Two facades in making use of platform-based design methodology Two facades in making use of platform-based design methodology First façade First façade Identification of the key functions in target application set by using profiling techniques. Identification of the key functions in target application set by using profiling techniques. Second façade Second façade The exploration of architectural module The exploration of architectural module Execution Execution Phase I : Identify a set of possible architectures for the target applications Phase I : Identify a set of possible architectures for the target applications Phase II : Explore how effectively the kernel functions are supported by these architectures Phase II : Explore how effectively the kernel functions are supported by these architectures

8 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab 3. FUNCTIONAL KERNELS OF WIRELESS PROTOCOL STACKS The key operations in protocol processing The key operations in protocol processing Classification in the nature of the algorithm Classification in the nature of the algorithm Control processing Control processing Data processing Data processing Operations are directly on the feed forward path through the communication pipeline Operations are directly on the feed forward path through the communication pipeline Demanding real-time performance constraints Demanding real-time performance constraints Control processing Control processing Operation are not directly path Operation are not directly path Demanding looser timing constraints Demanding looser timing constraints

9 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Two facades in making use of platform-based design methodology Two facades in making use of platform-based design methodology First façade First façade Identification of the key functions in target application set by using profiling techniques. Identification of the key functions in target application set by using profiling techniques. Second façade Second façade The exploration of architectural module The exploration of architectural module Execution Execution Phase I : Identify a set of possible architectures for the target applications Phase I : Identify a set of possible architectures for the target applications Phase II : Explore how effectively the kernel functions are supported by these architectures Phase II : Explore how effectively the kernel functions are supported by these architectures

10 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab 4. RECONFIGURABLE FABRIC Definition of architectures Definition of architectures A class of architectures that offer a unique balance between hardware and software design implementation A class of architectures that offer a unique balance between hardware and software design implementation Requirement Requirement

11 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab FPGA(field programmable gate arrays) FPGA(field programmable gate arrays) CLB(configurable logic block) CLB(configurable logic block) Consist of LUTs and FFs arrays Consist of LUTs and FFs arrays

12 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab PAL(programmable array logic) PAL(programmable array logic) Consist of programmable AND arrays and fixed OR-arrays Consist of programmable AND arrays and fixed OR-arrays

13 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Comparison Comparison

14 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Hybrid structure Hybrid structure Mixed the FPGA and PAL Mixed the FPGA and PAL

15 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Block diagram of the PAL block in a hybrid block. Block diagram of the PAL block in a hybrid block.

16 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Block diagram of the FPGA block in the hybrid block. Block diagram of the FPGA block in the hybrid block.

17 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab The integration of the PAL and the FPGA. The integration of the PAL and the FPGA.

18 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab The layout of the macrocell used in the low-energy PAL. The layout of the macrocell used in the low-energy PAL.

19 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab The layout of the PAL used in a hybrid block. The layout of the PAL used in a hybrid block.

20 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab The layout of the FPGA used in a hybrid block. The layout of the FPGA used in a hybrid block.

21 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab The layout of a hybrid block. The layout of a hybrid block.

22 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab 5. CONCLUSION PAL is using to implement control logic PAL is using to implement control logic FPGA is using to implement data logic FPGA is using to implement data logic So hibrid architecture consist of PAL and FPGA So hibrid architecture consist of PAL and FPGA

23 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab Normalized area comparison between the hybrid implementation vs. the non-hybrid implementations. Normalized area comparison between the hybrid implementation vs. the non-hybrid implementations.

24 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab APPENDIX A Various operations typically found in the different layers of a wireless protocol stack Application characteristics

25 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab APPENDIX B TCI low-level protocol in the Cadence VCC |CADENCE| environment, which consist of concurrent, extended finite state machines

26 IT-SOC 2002 © 스마트 모빌 컴퓨팅 Lab APPENDIX E Basic memory-based programmable logic with AD_OR planes. Each black dot indicates a connection Programmable Logic Devices