Day 16: October 6, 2014 Inverter Performance ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 16: October 6, 2014 Inverter Performance Penn ESE370 Fall2014 -- DeHon

Previously Delay as RC-charging Transistor Capacitance Drive Current As a function of geometry (W/L) Penn ESE370 Fall2014 -- DeHon

Today t-model Sizing Large Fanout Capacitance Revisited Miller Effect Parallel Gate Capacitance Penn ESE370 Fall2014 -- DeHon

Transistor Sizing What happens to Ids as a function of W? What happens to Cg as a function of W? Conclude: faster transistors present more load on their inputs Penn ESE370 Fall2014 -- DeHon

First Order Delay R0 = Resistance of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Rdrive = R0/W Cg = WC0 Penn ESE370 Fall2014 -- DeHon

First Order Delay (alt view) I0 = Ids of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Idrive = WI0 Cg = WC0 Penn ESE370 Fall2014 -- DeHon

t model All delays are RC delays (CV/I delays) Always have an R0C0 term (C/I term) t = R0C0 (equivalently C0/I0) Express all delays in t units Like l units for measurement Separate delay into Technology dependent term t = R0C0 Technology independent term Penn ESE370 Fall2014 -- DeHon

Inverter Sizing What is the impact of the delay on the middle inverter if double size of all the transistors? Penn ESE370 Fall2014 -- DeHon

How Size How size to equalize Rise and Fall? mn=500cm2/Vs, mp=200cm2/Vs When velocity saturated Rdrive=R0/2 (Idrive=2I0) Not velocity saturated Ids=(mCOX/2)(W/L)(Vgs-VTH)2 Penn ESE370 Fall2014 -- DeHon

SPICE Simulation Penn ESE370 Fall2014 -- DeHon

SPICE Simulation 22nm Penn ESE370 Fall2014 -- DeHon

Worst Case Delay Largest R Rdrive = max(Rpullup,Rpulldown) If equalize Rpullup and Rpulldown Rdrive = Rpullup=Rpulldown Penn ESE370 Fall2014 -- DeHon

Equalizing Delay For simplicity, for today Assume Wp=Wn equalizes Ids Penn ESE370 Fall2014 -- DeHon

Multistage Delay Total delay = sum of stage delays What is delay here? From (P1,N1) to final capacitive load Penn ESE370 Fall2014 -- DeHon

Large Fanout What is delay if must drive fanout=100? Penn ESE370 Fall2014 -- DeHon

What Delay? What is delay here? Penn ESE370 Fall2014 -- DeHon

How Size How size transistors to minimize delay? Penn ESE370 Fall2014 -- DeHon

Optimizing Delay = 2Wmid/1 + 200/Wmid How minimize? D(Delay)/D(Wmid) = 0 2 – 200/(Wmid)2=0 Wmid=sqrt(100) = 10 Penn ESE370 Fall2014 -- DeHon

Delay? Delay at optimal Wmid? Penn ESE370 Fall2014 -- DeHon

Try again What is the delay here? Penn ESE370 Fall2014 -- DeHon

…and Again Delay here? Penn ESE370 Fall2014 -- DeHon

Lesson Don’t drive large fanout with a single stage Must scale up over a number of stages …but not too many Exact number will be technology dependent Penn ESE370 Fall2014 -- DeHon

Charge on Capacitors Penn ESE370 Fall2014 -- DeHon

Questions What is DQ when switched? Equivalent Capacitance? Contribution from each transistor? Penn ESE370 Fall2014 -- DeHon

Gate-Drain Capacitance What is the voltage across Vin—V2 When Vin=Vdd When Vin=Gnd What is DV across Vin—V2 when Vin switches from Vdd to Gnd? Penn ESE370 Fall2014 -- DeHon

Miller Effect For an inverting gate Capacitance between input and output must swing 2 Vhigh Or…acts as double-sized capacitor Penn ESE370 Fall2014 -- DeHon

Ideas First order delay reason in t=R0C0 units Equivalently (C0/I0) units Scaling everything up doesn’t help Drive large capacitive loads in stages Penn ESE370 Fall2014 -- DeHon

FPGA Architecture and Design Admin HW5 due Tuesday Talk Today at 2pm in Towne 337 Mike Hutton (Altera) FPGA Architecture and Design Penn ESE370 Fall2014 -- DeHon