STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.

Slides:



Advertisements
Similar presentations
Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.
Advertisements

COMBINATIONAL LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
Static CMOS Circuits.
Logic Gates.
CMOS Layers n-well process p-well process Twin-tub process ravikishore.
Digital Integrated Circuits© Prentice Hall 1995 Design Rules Jan M. Rabaey Design Rules.
Documentation Standards
VLSI Design Circuits & Layout
Experiment #2: Introduction to Logic Functions and their Gate-Level Hardware Implementations CPE 169 Digital Design Laboratory.
Prelab: MOS gates and layout
Combinational MOS Logic Circuit
Salman Zaffar IqraUniversity, Spring 2012
7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.
Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.
VLSI Design Circuits & Layout
Introduction to CMOS VLSI Design Circuits & Layout
ENGG 1203 Tutorial Combinational Logic (I) 1 Feb Learning Objectives
Module-3 (MOS designs,Stick Diagrams,Designrules)
Complementary CMOS Logic Style Construction (cont.) Digital Integrated Circuits© Prentice Hall 1995 Introduction.
Complementary CMOS Logic Style Construction (cont.)
Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Design rules and fabrication. n SCMOS scalable design rules. n Stick.
1 Euler Graph Using Euler graph to draw layout. 2 Graph Representation Graph consists of vertices and edges. Circuit node = vertex. Transistor = edge.
Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 14: October 1, 2014 Layout and.
Notices You have 18 more days to complete your final project!
Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 5, 2011 Layout and.
EE4800 CMOS Digital IC Design & Analysis
Modern VLSI Design 3e: Chapter 2Partly from 2002 Prentice Hall PTR week4-1 Lecture 10 Wire and Via Jan. 27, 2003.
VLSI Design Lecture 4-b: Layout Extraction Mohammad Arjomand CE Department Sharif Univ. of Tech.
Introduction EE1411 Design Rules. EE1412 3D Perspective Polysilicon Aluminum.
STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.
Purpose of design rules:
1 Contents Reviewed Rabaey CH 3, 4, and 6. 2 Physical Structure of MOS Transistors: the NMOS [Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.
Logic Gates. AND gate Produces an output only if both inputs are on Input AInput BOutput (Q) Q=
ENG241/ Lab #11 ENG2410 Digital Design LAB #1 Introduction Combinational Logic Design.
Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 LECTURE 9: KEEE 4425 WEEK 7 CMOS LAYOUT AND STICK DIAGRAM (Cont’d)
Static CMOS Logic Seating chart updates
Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-1 Panorama of VLSI Design Fabrication (Chem, physics) Technology (EE) Systems (CS) Matel.
STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.
EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, nd rev. : April 10, 2003.
Stick Diagrams Stick Diagrams electronics.
CSE477 L06 Static CMOS Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 06: Static CMOS Logic Mary Jane Irwin (
Cell Design Standard Cells Datapath Cells General purpose logic
Full-Custom Design ….TYWu
S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal
CHAPTER 4: MOS AND CMOS IC DESIGN
Day 12: October 4, 2010 Layout and Area
FIGURE 3.1 Two-variable K-map
THE CMOS INVERTER.
The MOS Transistor Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996.
Layout of CMOS Circuits
Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56
STICK Diagrams UNIT III : VLSI CIRCUIT DESIGN PROCESSES VLSI DESIGN
VLSI System Design Lecture: 1.3 COMS LOGICs
Design Rules.
COMBINATIONAL LOGIC.
Layout of CMOS VLSI Circuits
Layout of CMOS VLSI Circuits
VLSI Lay-out Design.
VLSI Design CMOS Layout
Where are we? Lots of Layout issues Line of diffusion style
V.Navaneethakrishnan Dept. of ECE, CCET
COMBINATIONAL LOGIC DESIGN
UNIT-II Stick Diagrams
EENG447 Digital IC Design Dr. Gürtaç Yemişcioğlu.
ECE 424 – Introduction to VLSI Design
Digital Logic Experiment
CMOS Layers n-well process p-well process Twin-tub process.
Chapter 6 (I) CMOS Layout of Complexe Gate
Presentation transcript:

STICK DIAGRAM EMT251

Schematic vs Layout In Out V DD GND Inverter circuit

Schematic vs Layout A Out V DD GND B 2-input NAND gate

Stick Diagram A stick diagram is a graphical view of a layout. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

Stick Diagram Represents relative positions of transistors Stick diagrams help plan layout quickly  Need not be to scale  Draw with color pencils or dry-erase markers In Out V DD GND Inverter A Out V DD GND B NAND2

Stick Diagram Metal (BLUE) Polysilicion (RED) N-Diffusion (Green) P-Diffusion (Brown) Contact / Via Layers

Figure 1: Schematic and Graph

Figure 2: Euler Path

Figure 3: Connection label layout 1 2

Figure 4: VDD, VSS and Output Labels 1 2

Figure 5: Stick Diagram, Interconnected Reference: Chapter 4, Appendix C, Digital Integrated Circuits, Jan M. Rabaey 1 2

Exercise 1 A B C Logic Gate A X = C (A + B) B A C C B i j

Solution: Stick Diagram of C (A + B) ABC X V DD GND

Exercise 2 A B C D X = (A+B)(C+D) D C C AB B A D Logic Gate

Thank you