RPC Upscope Meeting Jay Hauser 05 Feb 20101/11 Overview of the CSC Phase I Upgrade plans ME4/2 upgrade: 72 new large chambers for high-luminosity triggering in  Flash ADC board for cathode digitization ME1/1 to handle high rates ME1/1 to restore trigger and improve reconstruction for  Upgrade ME1/1 associated TMB and DMB boards Schedule and “to-do” list

RPC Upscope Meeting Jay Hauser 05 Feb 20102/11 ME4/2 and ME1/1 upgrades R-Z cross-section “Empty” YE3 disk ready for ME4/2

RPC Upscope Meeting Jay Hauser 05 Feb 20103/11 ME4/2 upgrade motivation Triggering with & without the ME4/2 upgrade: The high-luminosity Level 1 trigger threshold is reduced from 48  18 GeV/c Target Rate 5 kHz Ingo Bloch, Norbert Neumeister, Rick Wilkinson

Simulation result (May ’09) ( Vadim Khotilovich, Alexei Safonov) Efficiency gaps for good quality TF tracks disappear with addition of ME4/2

RPC Upscope Meeting Jay Hauser 05 Feb 20105/11 “Digital CFEB” cathode board CSC principle: digitize cathode charges to ~1%, interpolate for fine position Current CFEB: the ADC is multiplexed 16:1 Requires analog charge storage ASIC (SCA) Serial digitization after L1A Digital CFEB uses Flash ADCs: Continuous and deadtimeless digitization pre SCA ADC + - ref 16 FPGA 12 bits muxmux 21 bits Chan- link 21:3 To DMB over Skewclear 280 Mbps 6 layers pre ADC + - ref 16 FPGA 8 pairs layers Serial Opt. Trnscvr To DMB over Fiber ~1Gbps MGT ADC ref 8 pairs 16 pairs Pipeline/FIFOs Serial LVDS

RPC Upscope Meeting Jay Hauser 05 Feb 20106/11 ME1/1 Restoration of  High-  section of ME1/1 Cathode strips are currently ganged 3:1 Plan: Install DCFEB boards on ME1/1 Move existing CFEBs from ME1/1 to ME4/2 Takes ~2.5 months per endcap 72 new TMB and DMB boards needed to accommodate additional inputs, optolinks Channel 16 … Electronics Channel 1 … … Strips: …

US-CMS CD0 group Jay Hauser 24 Feb DMB/TMB modifications Needed for 72 ME1/1 chambers: Option for 7 DCFEBs/chamber requires optical links I/O More reliable than Skewclear copper Requires more FPGA space and faster processing in TMB (mezzanine card Virtex2  Virtex6 ) Skewclear-SCSI connectors DMB TMB

RPC Upscope Meeting Jay Hauser 05 Feb 20108/11 ME4/2 Planning : a ME4/2 prototype chamber was built at FNAL and installed at CERN same design as ME2/2 and ME3/2 but some critical vendors and parts have changed installed in CMS with 4 spare chambers for “battle testing” working fine Qualification of additional parts vendors (especially FR4 skins) Production plans are well understood, but funding t 0 not yet established Otherwise, the B904 plan seems to be taking shape

RPC Upscope Meeting Jay Hauser 05 Feb 20109/11 ME4/2 Upgrade Schedule t months CD2 approval, money flows, begin work on Bldg 904 t months orders sent out for all parts t months production tooling shipped to CERN and assembled in Bldg 904 t months chamber parts delivered, shipped to CERN t months production begins at Bldg 904 at 2 CSCs/month t months production ramps to 4 CSCs/month t months FAST site begins assembly & testing at CERN (Bldg 904?), spare CFEB boards installed on ME4/2s t months 42 CSCs finished and tested -- ready for installation of 1st endcap, recover 200 CFEB boards from ME1/1s t months all 76 CSCs finished t months final 36 chambers ready for installation on 2nd endcap

RPC Upscope Meeting Jay Hauser 05 Feb /11 Overall schedule (if FY2011 start)

RPC Upscope Meeting Jay Hauser 05 Feb /11 Muon upgrade to-do list DCFEB first prototype ready soon (~April) Could DCFEBs be installed in 2012 on ME1/1? If funded and pushed… Design started on other associated electronics upgrades for ME1/1 TMB and DMB boards hardware and firmware Chamber assembly: B904 assembly area currently being developed ~May send FNAL assembly machines to CERN Later in 2010 send parts for several chambers to CERN, use these to develop assembly space and train factory personnel (depends on production t 0 )

RPC Upscope Meeting Jay Hauser 05 Feb /11 Backup Slides

US-CMS CD0 group Jay Hauser 24 Feb New ALCT mezzanine card prototype Gbps optical transceiver Serializer Deserializer FPGA XC4VLX25-11FF668 Link reference oscillator Front-end Clock and Time marker Reset inputs Inputs from front-end discriminators Gbps eye diagram (receiver’s electrical output after 100 m of fiber) MTCC data: from KeyWireGroup to WeightedWireGroup Position resolution improvement:Position resolution improvement: Prototype:Prototype: Alex Madorsky

US-CMS CD0 group Jay Hauser 24 Feb Neutron backgrounds: a typical event at LHC        From 1999 study using Gamma Irradiation Facility Study of LHC-like neutron background conditions (gamma ray source) One event, 6 layers, charge per strip as a function of time (into page) 10x higher backgrounds will give quite substantial occupancy… Clearly, simulations are crucial

US-CMS CD0 group Jay Hauser 24 Feb Muon Port Card upgrade Currently MPC  Sector Processor limited to 3 CSC stubs per 60 degree sector High Pt muon plus low-Pt muons or accidentals can lose muon stubs Efficiency loss grows dramatically with luminosity Phase 1 replacement of Sector Processors: Optical links >10 Gb data transfer rate (vs. 1.6 Gb) Other end of links (MPCs) must also be upgraded MPC replacement (60 boards): ser/des can reduce CSC muon stub bottleneck further use faster FPGA to maintain current latency

EMU/ME1/1 meeting 25 February,2008, V.Karjavin Read out integration issues: ?

EMU/ME1/1 meeting 25 February,2008, V.Karjavin On-chamber integration issues:  Cooling plates of stay the same - Design of the new covers and fixtures for CFEBs - Replacement of the cooling pads  Replacement of the “3 to 1” R/O back to 3 CFEBs  On chamber cabling: - input cables from CSC to CFEB for ME1/1b stay the same - Procurement of the new input cables from CSC to CFEB for ME1/1a - LV cables stay the same (length should be confirmed) ME1/1b ME1/1a

EMU/ME1/1 meeting 25 February,2008, V.Karjavin Off-chamber integration issues: Output from CSC – for optics better to locate patch panel 2. Cables excess storage place – loops for optics must be foreseen 3.Input in vertical trays (covered by ME2,3 chambers) – scenarios for optic cables installation (dismantle skewclear cables?)

EMU/ME1/1 meeting 25 February,2008, V.Karjavin Off-chamber integration issues:  Redesign of ME1/1 Patch panel - Dismantle skewclear cables - Fixation of optic cables - Optics connection to chamber – patch panel?

RPC Upscope Meeting Jay Hauser 05 Feb /11 Phase 2 upgrade To-Do items Understand background rates from real data Understand implications of backgrounds: Trigger rates, data bottlenecks, performance degradation SEU rates Electronics radiation hardness Understand implications of track trigger upgrade Understand benefits of better trigger primitive resolution