L19 – Resolved Signals

Resolved Signals  What are resolved signals In systems In VHDL Resolution – Isn’t that for resolving conflicts?  Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU2

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU3 Busses and Wires  What is the difference between a bus and a wire?  Wires – have only one driving source

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU4 Busses and Wires  Busses, on the other hand, can be driven by one or more sources  In both cases, wires and busses, there can be more than one destination for the signal  With busses, only the device acting as source will actually drive a value. All others will have their output set at high impedance (Z).

9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU5 How do you handle Busses in an HDL?  First must consider the information present on a wire and on a bus in a digital circuit.  Information present on a wire or bus: Wire is limited to 2 stable states Using TYPE BIT  High or 1 or ‘1’  Low or 0 or ‘0’ There is a transition period between the two but High and Low are the only 2 stable states.

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU6 Information on a Bus  Possible states for a BUS Driven high (driven to a 1) Driven low (driven to a 0) No driving value (Z or high impedance) Capacitive high (H) Capacitive low (L) Conflict (one driver driving it to a 1, another a 0) (X) Conflict of capacitive values (W)  And other useful values U – Uninitialized – - a Don’t Care

Type std_logic  Std_logic has 9 states TYPE std_ulogic IS ( ‘u’, --uninitialized ‘x’, --forcing unknown ‘0’, --forcing 0 ‘1’, --forcing 1 ‘Z’, --forcing 0 ‘W’, --weak unknown ‘L’, --weak 0 ‘H’, --weak 1 ‘-’ --don’t care ); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU7

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU8 In an HDL need Resolution  With multiple drivers of a signal how do you resolve the value seen by devices using the bus?  RESOLUTION How to determine the value when two or more drivers are driving the same signal  Must look at all drivers and determine the appropriate value to use.

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU9 The resolution function function resolved (s : mv4_logic_vector) RETURN mv4_logic IS variable result : mv4_logic := Z; – weakest state BEGIN IF (s’length = 1) then return s(s’low) ELSE FOR i IN s’range LOOP result := resolution_table(result,s(i)); END LOOP; END IF; return result; END resolved;  Execution could be shortened by adding exit when result=‘U’

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU10 The big picture(or the little picture)  After posting of a transaction(s) to the current value of one or more of the drivers, a vector composed of the current values of the drivers is sent to the resolution function for determination of the resolved value.

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU11 Completeness of a MVL package  Having a MVL type with resolution is only part of creating a MVL system.  ALSO need Overloaded function for standard operators Type conversion functions to convert from other type to this type and the reverse  ieee_1164 standard MVL package is a standard package for a multi-value logic system and contains all of these.

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU12 Use of Resolved signals  Must use a resolved signal type for any signals of mode INOUT PORT ( ABUS : INOUT mv4r_logic; …  Within an ARCHITECTURE they are needed whenever the signal will have more than one driver

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU13 Standard logic 1164  Package is online in the course directory but not on the course webpage  Opens with comments on the code  What is the first part of declaring an MVL system in a package?

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU14 Declaration Part of the Package  Declare MVL logic system types  Declare the resolution function  Declare the resolved type  And declare the array types for vectors  Declare subtype of reduced logic systems

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU15 Overload operators  All operators are overloaded  Can find the package in ~degroat/ee762_assign/ std_1164.vhd

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU16 Type conversion functions and edge detection  To convert from built in logic types of BIT and BIT_VECTOR  And there are similar conversion functions for the reduced logic systems  Also have functions for rising and falling edge

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU17 Now have the package body  Starts with a header  First code is for the resolution function  Note initial state  Note sink state Sink state is state that overrides all others

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU18 The various functions  The AND table  The OR table

1/8/ L17 Resolved Siganls Copyright Joanne DeGroat, ECE, OSU19 For operation on single logic values and vectors  Single values and vectors

Using std_logic in a design  Create a bus driver and then set up 3 units driving the bus. Only 1-bit data. As 3 units have 3 control signals that control driving the data onto the bus line, drive1, drive2, drive3.  Again start with the HDL code. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU20

The HDL code for the bus driver  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY busdr IS  PORT (drive : IN std_logic;  data : IN std_logic;  intbus : OUT std_logic);  END busdr;  ARCHITECTURE one OF busdr IS  BEGIN  PROCESS (drive,data)  BEGIN  IF (drive='1') THEN intbus <= data;  ELSE intbus <= 'Z';  END IF;  END PROCESS;  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU21

Notes on using std_logic  First you must make the VHDL design library visible to the design unit.  This is done with the LIBRARY clause.  If the clause is before the ENITY then the Library is visible to the ENTITY and all ARCHITECTURES of the ENTITY If it were before the ARCHITECTURE then the library is visible only to that ARCHITECTURE 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU22

The USE clause  To use the declarations, functions, and procedures of a package you must give access to them. This is done through a USE clause which has same visibility rules as LIBRARY clause.  USE library.packagename.all provides access to all the declarations of the PACKAGE declarative part. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU23

Back to bus driver  Make std_logic useable  Bus driver interface Data input Bus connection Drive control – when asserted data driven onto bus – otherwise Z  ARCHITECTURE implements behavior.  Done with an if statement in a PROCESS  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY busdr IS  PORT (drive : IN std_logic;  data : IN std_logic;  intbus : OUT std_logic);  END busdr;  ARCHITECTURE one OF busdr IS  BEGIN  PROCESS (drive,data)  BEGIN  IF (drive='1') THEN intbus <= data;  ELSE intbus <= 'Z';  END IF;  END PROCESS;  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU24

Using the bus driver  Connect multiple sources than can generate information  Here 3 drivers of the bus.  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY mdrv IS  PORT (intbus : INOUT std_logic);  END mdrv;  ARCHITECTURE one OF mdrv IS  COMPONENT busdr IS  PORT (drive : IN std_logic;  data : IN std_logic;  intbus : OUT std_logic);  END COMPONENT;  FOR all : busdr USE ENTITY work.busdr(one);  --internal signals  SIGNAL dr1,dr2,dr3 : std_logic;  SIGNAL data1,data2,data3 : std_logic;  BEGIN  u1 : busdr PORT MAP (dr1,data1,intbus);  u2 : busdr PORT MAP (dr2,data2,intbus);  u3 : busdr PORT MAP (dr3,data3,intbus);  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU25

And then synthesize it in Quartis  What does an FPGA tool do with this? 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU26

The results  3 single bit driving units connect to one bus line  Within the 3 boxes in the top figure you have a tristate driver. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU27

Keys to having Quartis work  Project has name pnm  Top level VHDL file is pnm.vhdl  In the VHDL code it is “ENTITY pnm IS …” 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU28

Extending the one bit to 8  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY busdr IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END busdr;  ARCHITECTURE one OF busdr IS  BEGIN  PROCESS (drive,data)  BEGIN  IF (drive='1') THEN intbus <= data;  ELSE intbus <= "ZZZZZZZZ";  END IF;  END PROCESS;  END one;  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY mdrv IS  PORT (intbus : INOUT std_logic_vector(7 downto 0));  END mdrv;  ARCHITECTURE one OF mdrv IS  COMPONENT busdr8 IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END COMPONENT;  FOR all : busdr8 USE ENTITY work.busdr(one);  --internal signals  SIGNAL dr1,dr2,dr3 : std_logic;  SIGNAL data1,data2,data3 : std_logic_vector(7 downto 0);  BEGIN  u1 : busdr8 PORT MAP (dr1,data1,intbus);  u2 : busdr8 PORT MAP (dr2,data2,intbus);  u3 : busdr8 PORT MAP (dr3,data3,intbus);  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU29

Notes on extension  The only change was to the data and bus size – from single bit to 8-bits 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU30

Now adding a register  The register HDL code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY reg8 IS PORT (datain : IN std_logic_vector(7 downto 0); load : IN std_logic; dataout : OUT std_logic_vector(7 downto 0)); END reg8; ARCHITECTURE one OF reg8 IS BEGIN PROCESS (datain,load) BEGIN IF (load='1' AND load'event) THEN dataout <= datain; END IF; Synthesis results: END PROCESS; LUTS – 0 Registers – 8 Pins – 17 END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU31

Putting them together  Now desire to add the register to the bus driver  Need 3 segments of VHDL code Code for the registers 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU32

Register code  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY reg8 IS  PORT (datain : IN std_logic_vector(7 downto 0);  load : IN std_logic;  dataout : OUT std_logic_vector(7 downto 0));  END reg8;  ARCHITECTURE one OF reg8 IS  BEGIN  PROCESS (datain,load)  BEGIN  IF (load='1' AND load'event)  THEN dataout <= datain;  END IF;  END PROCESS;  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU33

Bus driver code  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY busdr IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END busdr;  ARCHITECTURE one OF busdr IS  BEGIN  PROCESS (drive,data)  BEGIN  IF (drive='1') THEN intbus <= data;  ELSE intbus <= "ZZZZZZZZ";  END IF;  END PROCESS;  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU34

The total code – 3 instances reg8  LIBRARY IEEE;  USE IEEE.STD_LOGIC_1164.all;  ENTITY regmdrv8 IS  PORT (intbus : INOUT std_logic_vector(7 downto 0));  END regmdrv8;  ARCHITECTURE one OF regmdrv8 IS  COMPONENT busdr8 IS  PORT (drive : IN std_logic;  data : IN std_logic_vector(7 downto 0);  intbus : OUT std_logic_vector(7 downto 0));  END COMPONENT;  FOR all : busdr8 USE ENTITY work.busdr8(one);  COMPONENT reg8 IS  PORT (datain : IN std_logic_vector(7 downto 0);  load : IN std_logic;  dataout : OUT std_logic_vector(7 downto 0));  END COMPONENT;  FOR all : reg8 USE ENTITY work.reg8(one);  --internal signals  SIGNAL l1,l2,l3 : std_logic;  SIGNAL dr1,dr2,dr3 : std_logic;  SIGNAL data1,data2,data3 : std_logic_vector(7 downto 0);  SIGNAL datai1,datai2,datai3 : std_logic_vector(7 downto 0);  BEGIN  u1 : busdr8 PORT MAP (dr1,data1,intbus);  u2 : busdr8 PORT MAP (dr2,data2,intbus);  u3 : busdr8 PORT MAP (dr3,data3,intbus);  r1 : reg8 PORT MAP (datai1,l1,data1);  r2 : reg8 PORT MAP (datai2,l1,data2);  r3 : reg8 PORT MAP (datai3,l1,data3);  END one; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU35

Quartis results  Registers with bus drivers 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU36

The objective  Dual ported register set 2 data busses Can load or drive either bus No timing – only control  To insure this unit will synthesize need to do it subcomponent by subcomponent and structurally. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU37

Lecture summary  TYPE std_logic  Using std_logic to build into creating a register set  Next step – class input??? 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU38