7-8 BUS-Based Transfer A more efficient scheme for transferring data between registers is a system that shared transfer path called BUS. A block diagram for transfer between three registers ; Three n-bit 2-to-1 MUX 가 있음. ; Each MUX has select signal. ; Each register has its own LOAD signal Fig.7-19

Single BUS (Fig.7-19) The same system based on a BUS can be implemented by using a single n-bit 3-to-1 MUX and parallel load register. Single BUS

Single BUS를 이용한 transfer에 대한 예제 Register Transfer Select S1 S0 Load L2 L1 L0 R0  R2 1 0 0 0 1 R0  R1, R2  R1 0 1 1 0 1 R0  R1, R1  R0 Impossible 세 번째 예는 in a single clock cycle 에서는 불가능 since it requires simultaneous sources R0, R1, on the single BUS. 따라 서 두 개의 BUS 혹은 Fig.7-19 (a) 와 같은 dedicated MUX 가 필요.

MUX와 BUS의 비교 (H/W 측면에서) Fig.7-19 (a) 의 MUX 의 경우 ; 2n AND gates and n OR gate, for total of 9n AND gates Fig.7-19(b) 의 MUX 의 경우 ; 3n AND gates and n OR gate, for total of 4n gates

Three-State Buffers Two of the states are logic "1" and logic "0". The third state is high-impedance(Hi- Z) state. ; Behave like an open-circuit. 즉 출력 이 disconnected 된 것처럼 보임. If EN = 1, OUT is equal to IN. If EN = 0. OUT is Hi-Z, regardless of the value IN. Logic Symbol Truth Table

3 상태 버퍼를 사용하여 구성한 다중출력선 OL (Fig.2-34) 3 state-Buffer의 출력은 다중화 출력이 가능하도록 서로 연결될 수 있다.

Multiplexed Output of 3-state Buffer This conflict results in electrical current flowing from the buffer output that is at "1" into the buffer output that is at "0". 이 전류는 회로에 열을 발생시킬 정도로 커서 회로를 손상시킬 수 있다. BUS를 이러한 구조를 이용하여 설계할 경우 주의 할 점. 1. EN1 = EN0 = 1 이 되는 것을 피할 것. 오직 하나의 EN 만이 “1”이 되게 하고, 나머지 EN은 “0” 으로 할 것. 2. Decoder를 사용하여 EN 신호를 발생시키면 됨. 3. A set of n three-state buffers with their outputs connected together and EN inputs driven by a decoder provides n-to-1 selection, just as an n-to-1 line multiplexer does. RAM chip들의 출력에 이러한 three-state buffer를 사용하게 되면, RAM 출력에 연결된 bit line 으로부터 읽혀지는 chip들로부터 word를 얻어낼 수 있 다. chip select 가 EN 신호에 해당된다.

Tri-State Buffer

Three-State BUS BUS can be constructed with the three-state buffers instead of MUX 왜 ? ; Many tri-state buffer outputs can be connected to form a bit line of BUS and this bus is implemented using only one level of logic gates. 반면에 MUX의 경우 ; Such a large number of sources means a high fan-in OR, which requires multiple levels of OR gates, introducing more logic and increasing delay. Tri-state buffer 의 경우 Signals can travel in two directions . 즉 양방향으로 사용 가능하다. ; Fig.7-20 (a) 참조 ; If the buffers are enabled, then the lines are outputs. If the buffers are disabled, then the lines are inputs.

Tri-State BUS와 Multiplexer BUS 를 사용한 경우 비교 (Fig.7-20) Six data connections per bit to the set of register block. Three data connections per bit to the set of register block.

7-9 Serial Transfer & Microoperation C input = Shift + Clock Shift determines when and how many times the registers are shifted. Block diagram Timing diagram

Serial Transfer Example (표7-14)

Serial Addition (Fig.7-22) One Full Adder, One F/F for carry, and Two Shift Registers

Serial Addition (Fig.7-22) - Parallel 과 Serial Adders의 space-time trade-off. ; P-adder in space is n times larger than the S-adder, but it is n times faster. S-adder, although it is n times slower, is n times smaller in space.

Serial Addition (Fig.7-22)