Module 11 Adapted By and Prepared James Tan © 2001

Objectives In this lecture we will be looking at : M6802 Instruction Set Problem solving thru Assembly Language Programming

Table 3 List all instructions which involve either Accumulator A or Accumulator B Example: ADDA Include all instructions which operates directly on the contents of a memory location. Example: CLR ‘M’

Table 4 Include all instructions which operate on the contents of either the ‘index register’ or the ‘stack pointer’.

Table 5 Complete list of Branch and Jump instructions.

Table 6 Instructions for manipulating the content of condition code register.

Problem Solving Technique (pg 11.24) Step 1 – A flow Chart Step 2 – A Memory Map [Step 3 & 4: see page 11.25’s table] Step 3 – The assembly Language Section Step 4 – The Machine Coded Section

Programming Example 1 Evaluate 9 – Answer: Page to page 11.27

Programming Example 2 We will skip this in lecture, but please go thru yourself

Chapter 13 Learning Objectives: –Learn how to interface microprocessor to a peripheral device –Explain the normal operation of PIA –Keyboard & display interfacing –Understand DMA & interrupts

13.1 Introduction Microcomputers are ‘Bus Structured system’ which comprises: –Unidirectional Address Bus –Bi-directional Data Bus –Control Bus for read/write…etc M6802 has –16 Address lines (64K address space) –8 Data Lines –9 Control lines for memory read/write, clock signal and special controls.

Figure 13.1 Micro-computer System MicroprocessorClock RAM ROM DAC or ADC Peripheral Interface 1 Peripheral Interface 2 Keyboard & Digital Display Control Bus Bi-directional Data Bus Address Bus

Peripheral Interface Notice that the peripheral Interface is one that makes the CPU very useful. Common peripherals are keyboard, display device, secondary memory devices (e.g. floppy diskette drive). In some cases, there may be a need for an external device to access the CPU memory directly so as to speed up an operation: use DMA. –Example of DMA –CPU release control of all activity to a DMA controller, which is a device capable of transferring a large block of data to be save into a floppy diskette.

13.2 The Peripheral Interface Adapter MC6821 PIA –16 Data lines –4 I/O Control lines 16 data lines can be individually programmed as I/O. 2 of the control lines can be either inputs or outputs, and the other 2 can only be inputs.

How does PIA talk to MPU? Example: Keyboard which to transfer a key pressed to MPU via the PIA Keyboard PIA ‘A’ Key Pressed MPU Interrupt Interrupt Service Routine Display Store ‘A’ Display ‘A’

PIA Internal Structure (page 13.5) A Section Control Register (CRA) Data Direction Register (DDRA) Data Register (DRA) (aka Peripheral Register PRA) B Section Control Register (CRB) Data Direction Register (DDRB) Data Register (DRB) (aka Peripheral Register PRB)

Programming the PIA PA0 to PA7 can be program as input or output depending on content of 8-bit DDRA. –Logic ‘0’  input to the MPU side –Logic ‘1’  output to the peripheral side

PIA Read/Write Operation During MPU Read operation –Peripheral  PIA  MPU data bus During MPU Write operation –MPU  PIA Data Register  PIA outputs

PIA Section B Can also be programmed as inputs or outputs. However, the output are ‘tri-state’ buffers which allows the peripheral data lines to be in a high impedance mode when they are used as inputs. Tristate buffer: Low, High, high impedance state.

Control lines CA1 and CB1 Can only be inputs. Usually used to create interrupt for the MPU. They set the interrupt flags of the control register CRA and CRB. The Active transition desired (i.e.  or  )on CA1 and CB1 can be programmed by the two control register (CRA and CRB).

Peripheral Control CA2 Can be programmed as ‘interrupt input’ or a ‘peripheral control output’. Output compatible with TTL logic. Programmed by Control Register A (CRA)

Peripheral Control CB2 Can be programmed by Control Register B (CRB) as input or output. If programmed as input, it has high input impedance. If programmed as output, it can switch an external transistor directly.

PIA Block Diagram See Page 13.7

B-directional Data Lines (D0 – D7) Allow transfer of Data between MPU and PIA. Data output bus driver are tristate and remain in a high impedance (OFF) state except when the MPU performs a read operation. The Read/Write (R/W) line is in the read (high) state when PIA is selected for a Read operation.

Enable The main timing signal derived from clock. All data transfer are referenced to this signal.

Read/Write (R/W) R/W = low  enable input buffers MPU –- data  PIA R/W = high  enable PIA to MPU transfer.

A LOW state reset all register bits in the PIA to zero. Can be used as power on reset or master reset signal.

PIA Chip Select ___ Designated as CS 0, CS 1, CS 2 To select the MPU for the MPU to access CS 0 = 1 CS 1 = 1 ____ CS 2 = 0

PIA Register Select RS 0 and RS 1 are designated to select various registers inside the PIA.

_____ _____ Interrupt Request ( IRQA or IRQB) Used to interrupt MPU. Can be direct interrupt or thru some priority scheme. » _____ Either CB1 or CB2 can cause the IRQB line to go low from the control registers. The MPU may then read the control registers by some software routine. Flags are cleared (0) as a result of MPU read and after being cleared can’t be set again until after an e pulse cycle.

End of Lecture