DATA TYPES 1.Pre-Defined Data Types 2. User-Defined Data Types.

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Presentation transcript:

DATA TYPES 1.Pre-Defined Data Types 2. User-Defined Data Types

VHDL contains a series of pre-defined data types which are specified through the IEEE 1076 and IEEE 1164 standards. Packages / libraries containing various data types 1.Package standard of library std :- It defines BIT, BOOLEAN, INTEGER and REAL data types. Ex: BIT (and BIT_VECTOR) :- 2-LEVEL LOGIC (‘0’, ‘1’) SIGNAL X: BIT X<= ‘1’; SIGNAL Y: BIT_VECTOR ( 3 down to 0 ); Y<= “1100”; SIGNAL W: BIT_VECTOR( 0 TO 7 ); W <= ; --(MSB=1)

BOOLEAN: TRUE, False. INTEGER: 32 bit integer (from to ) REAL: From -1.0E38 to +1.0E38 ( not synthesizable)

Package std_logic_1164 of library ieee It defines STD_LOGIC and STD_ULOGIC datatypes. STD_LOGIC (and STD_LOGIC_VECTOR): 8 valued logic system introduced in the IEEE 1164 standard. ‘X’ Forcing unknown (synthesizable unknown) ‘0’ Forcing Low (synthesizable logic ‘0’) ‘1’ Forcing High (synthesizable logic ‘1’) ‘Z’ High impedance (synthesizable tri-state buffer)

‘W’ Weak unknown ‘L’ Weak low ‘H’ Weak high ‘-’ Don’t care These four logic levels are intended for simulation only. The multiple driven nodes are resolved in favor of forcing values with respect to the weak values.

In STD_LOGIC, the conflicting logic levels are resolved according to following table X01ZWLH- XXXXXXXXX 0X0X0000X 1XX11111X ZX01ZWLHX WX01WWWWX LX01LWLWX HX01HWWHX -XXXXXXXX

It includes an extra logic value, ‘U’ which stands for unresolved. In this conflicting logic levels are not automatically resolved, so output wires should never be connected together directly. It is used to detect design errors. STD_ULOGIC (STD_ULOGIC_VECTOR) :- 9-Level logic system introduced in the IEEE 1164 standard (‘U’, ’X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’)