MICROPROCESSORS AND APPLICATIONS SNGCE MICROPROCESSORS AND APPLICATIONS Mr. DEEPAK P. Associate Professor ECE Department SNGCE DEEPAK.P DEEPAK P
SNGCE UNIT 1 DEEPAK.P DEEPAK P
Objective To study the architecture of microprocessors 8085 and 8086. To understand the instruction set of 8085. To know the methods of interfacing them to the peripheral devices. To use all the above in the design of microprocessor based systems. DEEPAK.P
Introduction to microcomputers 4 DEEPAK.P
Computer DEEPAK.P
Analog Computer The input data is not a number but a physical quantity like tem, pressure, speed, velocity. DEEPAK.P
Digital Computer Output Signals are two level of (0 V or 5 V) Memory Input CPU Output DEEPAK.P
Digital Computer The difference between main, mini, super and micro lies in the capacity and performance of the electronics used to implement their building blocks and the resulting overall system capacity and performance. DEEPAK.P
Main Frame Computer Occupies specially wired, air-conditioned rooms Capable of great processing speeds and data storage Not as powerful as supercomputers
Mini Computer It is a small general purpose system. These are more powerful and most useful as compared to micro computer. Mini computer are also known as mid range computer or Child computer. Application :- Departmental systems, Network Servers, work group system.
Super Computer High capacity Used by large organizations Tracking space Tracking weather
Micro Computer A Microcomputer is generally defined as computer based on a microprocessor. Microcomputers are single chip processors and are also known as PC’s (personal Computers). It is Least powerful and widely used computer Four types Desktop Notebook or laptop Tablet PC Handheld DEEPAK.P
Micro Computer Memory Input Microprocessor Output DEEPAK.P
Introduction to microprocessors 14 DEEPAK.P
Microprocessors The microprocessor is a semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale (LSI) or very-large-scale integration (VLSI) technique. The microprocessor, also known as the Central Processing Unit (CPU) if it is used in computers. DEEPAK.P
Microprocessors History DEEPAK.P
DATA FOR PROCESSING 17 DEEPAK.P
DATA FOR PROCESSING MICROPROCESSOR 18 DEEPAK.P
19 DEEPAK.P
LOWER ADDRESS /DATA BUS HIGHER ADDRESS BUS 20 DEEPAK.P
MEMORY 21 DEEPAK.P
PROCESSING ROOM CPU 22 DEEPAK.P
RAM ROM INPUT OUTPUT 23 DEEPAK.P
Basic Microprocessor DEEPAK.P
Microprocessor Based System DEEPAK.P
8085Microprocessors 26 DEEPAK.P
8085 Microprocessors DEEPAK.P
8085 Bus Structure DEEPAK.P
8085 Bus Structure DEEPAK.P
8085 Bus Structure The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory. It consists of 3 buses Address Bus.------ 16 bit Data Bus.--------8 bit Control and Status Signals.------8 bit The address bus has 8 signal lines A8 – A15 which are unidirectional. The other 8 address bits are multiplexed (time shared) with the 8 data bits. So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. DEEPAK.P
8085 Address and Data Bus Structure DEEPAK.P
8085 Bus Structure In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. DEEPAK.P
8085Microprocessor Architecture 16/7/14 DEEPAK.P 33
Microprocessor Architecture ALU DEEPAK.P
Microprocessor Architecture Interrupts DEEPAK.P
Microprocessor Architecture Interrupts When interrupt pin is activated, an ISR will be called, interrupting the program that is currently executing. INTR input is enabled when EI instruction is executed. DEEPAK.P
Microprocessor Architecture SID & SOD DEEPAK.P
Microprocessor Architecture SID & SOD DEEPAK.P
Microprocessor Architecture ALU In addition to the arithmetic & logic circuits, the ALU includes an accumulator, which is a part of every arithmetic & logic operation. Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer. DEEPAK.P
Microprocessor Architecture Flag Register Un used Un used Un used Auxiliary Carry Carry sign Zero Parity DEEPAK.P
Microprocessor Architecture Instruction Register Temporary store for the current instruction of a program. Decoder then takes instruction and ‘decodes’ or interprets the instruction. Decoded instruction then passed to next stage. Registers DEEPAK.P
Microprocessor Architecture Stack Pointer DEEPAK.P
Microprocessor Architecture Stack Pointer The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer. Eg. LXI SP, FFFF DEEPAK.P
Microprocessor Architecture Program Counter This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. DEEPAK.P
Microprocessor Architecture RESET RESET IN: an active low input signal, Program Counter (PC) will be set to 0 and thus MPU will reset. RESET OUT: an output reset signal to indicate that the μp was reset (i.e. RESET IN=0). It also used to reset external devices. DEEPAK.P
Microprocessor Architecture DEEPAK.P
Microprocessor Architecture Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. READY If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle. DEEPAK.P
Microprocessor Architecture HOLD; It indicates that another Master is requesting the use of the Address and Data Buses. HLDA It indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle RESET IN(Active Low) Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. DEEPAK.P
Microprocessor Architecture RESET OUT Indicates MP is being reset. Can be used as a system RESET for other peripherals. X1X2 Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency. DEEPAK.P
Microprocessor Architecture CLK (Output) Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. IO/M (Output) IO/M indicates whether the Read/Write is to memory or l/O DEEPAK.P
8085PIN DIAGRAM 18/7/14 DEEPAK.P 51
Pin configuration The 8085 is a complete 8 bit parallel central processor. It requires a single +5 volt supply. Its basic clock speed is 3 MHz Address bus is 16 bit(216 locations can be addressed) 216=65536 locations 1024 locations = 1 Kbytes So 216=65536 locations= 65536/1024=64 Kbytes DEEPAK.P
Pin configuration DEEPAK.P
Pin configuration DEEPAK.P
Pin configuration DEEPAK.P
Pin configuration The 8085 uses a multiplexed Data Bus. The address is split between the higher 8bit Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address is sent out. The lower 8bits are latched into the peripherals by the Address Latch Enable (ALE). DEEPAK.P
Pin configuration The 8085 provides RD, WR, and lO/Memory signals for bus control. The 8085 also provides serial input data (SID) and serial output data (SOD) lines for simple serial interface. The 8085 has three maskable, restart interrupts and one non-maskable trap interrupt. The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. DEEPAK.P
Pin configuration Decoded So, S1 Carries the following status information: DEEPAK.P
TRI STATE BUS 18/7/14 DEEPAK.P 59
Tristate Bus In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. DEEPAK.P
Tristate Bus DEEPAK.P
Tristate Buffer To separate the address from the data, we can use a Tristate latch. DEEPAK.P
GENERATION OF CONTROL SIGNAL 18/7/14 DEEPAK.P 63
Control and Status signals This group of signals includes two control signals (RD and WR), three status signals (IO/M, S1 and S0) to identify the nature of the operation. ALE (Address Latch Enable): This is a positive going pulse generated every time the 8085 begins an operation (machine cycle); it indicates that the bits on AD7-AD0 are address bits. This signal is used primarily to latch the low-order address from the multiplexed bus and generate a separate set of eight address lines, A7-A0. DEEPAK.P
Control and Status signals RD (Read): This is a Read control signal (Active Low). This signal indicates that the selected I/O or memory device is to be read and data are available on the data bus. WR (Write): This is a write control signal (Active Low). This signal indicates that the data on the data bus are to be written into a selected memory or I/O location. IO/M: This is a status signal used to differentiate between I/O and memory operations. When it is high, it indicates an I/O operation: when it is low, it indicates a memory operation. This signal is combined with RD (read) and WR (Write) to generate I/O and memory control signals. DEEPAK.P
Control and Status signals S1 and S0: These status signals, similar to IO/M, can be identify various operations, but they are rarely used in small systems. DEEPAK.P
Generating Control Signals DEEPAK.P
Generating Control Signals =0 1 Memory Read 1 RD=0 1 Memory Write WR=1 IO Read 1 IO Write 23-04-2013
Generating Control Signals =0 1 Memory Read RD=1 1 Memory Write 1 WR=0 IO Read IO Write 1 23-04-2013
Generating Control Signals =1 Memory Read 1 RD=0 Memory Write WR=1 1 IO Read 1 1 IO Write 23-04-2013
Generating Control Signals =1 Memory Read RD=1 Memory Write 1 WR=0 1 IO Read 1 IO Write 1 23-04-2013
De-multiplexing AD0-AD7 19/7/14 DEEPAK.P 72
De-multiplexing AD0-AD7 DEEPAK.P
De-multiplexing AD0-AD7 DEEPAK.P
De-multiplexing AD0-AD7 DEEPAK.P
De-multiplexing AD0-AD7 De multiplexing can be obtained by using a latch and ALE signal ALE (Address Latch Enable): This is a positive going pulse generated every time the 8085 begins an operation (machine cycle); it indicates that the bits on AD7-AD0 are address bits. When ALE is high, the tri state latch is enabled and lower order address is enabled(AD0-AD7 act as lower address bus) When ALE is low, the tri state latch is disabled AD0-AD7 act as data line) DEEPAK.P
PROCESSOR AND MECHINE CYCLE 21/7/14 DEEPAK.P 77
Processor cycle DEEPAK.P
Machine Cycle DEEPAK.P
Machine Cycle A separate operation performed by microprocessor is called machine cycle. MC1= Opcode Fetch---- 4/7 T states MC2= Memory Read, Memory write, I/O/read, I/O write------ 3 T states DEEPAK.P
INSTUCTION EXECUTION 21/7/14 DEEPAK.P 81
Instruction Execution Microprocessor reads the instruction byte by byte and then executes it. The instruction execution cycle can be clearly divided into three different parts Fetch Cycle The fetch cycle takes data required from memory, stores it in the instruction register. DEEPAK.P
Instruction execution Decode Cycle It determines which opcode and addressing mode have been used, and as such what actions need to be carried out in order to execute the instruction. Execute Cycle The actual actions which occur during the execute cycle of an instruction. DEEPAK.P
Instruction execution OPCODE Opcode is nothing but the machine language instruction which denotes the microprocessor about what operation should be performed on the specific data. OPERAND The data followed by opcode. DEEPAK.P
Instruction Execution 8085 instruction cycle includes Identify the memory location Generate timing and control signals Data transfer takes place Decoding the instruction Execution DEEPAK.P
1. Identify Memory Location DEEPAK.P
2. Generating Control Signals DEEPAK.P
3,4,5. Data flow from memory to microprocessor DEEPAK.P
3,4,5. Data flow from memory to microprocessor Memory usually starts at address 0000h and could go up to FFFFh (216 or 64K or 65536 in total). To access these locations, a 16 bit address is presented to memory and the byte at that location is either read or written. The Program Counter is what holds this address when the micro is executing instructions. DEEPAK.P
CODING OF AN INSTRUCTION 21/7/14 DEEPAK.P 90
8085 Instruction Instruction can be classified in to three according to size Single Byte Instruction MOV A,B Double Byte Instruction MVI A,08 Three Byte Instruction LDA 4500 To identify it , we have to code the instruction in to machine language DEEPAK.P
8085 Instruction Single Byte Instruction DEEPAK.P
8085 Instruction Double Byte Instruction DEEPAK.P
8085 Instruction Three Byte Instruction DEEPAK.P
8085 Instruction Coding Write a program to add two numbers and convert in to machine coding. Assume that user memory location starts from 4000 to 4FFF DEEPAK.P
TIMING DIAGRAMS 21/7/14 DEEPAK.P 96
Timing Diagram examples Timing diagram is the graphical representation of the initiation of read/write and transfer of data operations under the control of 3-status signals IO / M, S1, and S0. In 8085 , we have 5 machine cycles Opcode fetch Memory read Memory Write I/O read I/O write DEEPAK.P
Opcode Fetch cycle It is similar to memory read DEEPAK.P
Opcode Fetch cycle DEEPAK.P
Opcode fetch DEEPAK.P
Example Opcode fetch DEEPAK.P
Memory Read DEEPAK.P
Memory Read DEEPAK.P
Example Memory Read DEEPAK.P
Memory write DEEPAK.P
Example Memory write DEEPAK.P
I/O Read DEEPAK.P
I/O Write DEEPAK.P
TIMING DIAGRAMS example 23/7/14 DEEPAK.P 109
Timing Diagram INR M DEEPAK.P
Timing Diagram ADD M DEEPAK.P
Timing Diagram MVI B, Data DEEPAK.P
Timing Diagram IN, 8 bit address DEEPAK.P
Timing Diagram OUT, 8 bit address DEEPAK.P
Timing Diagram STA DEEPAK.P
Timing Diagram STA DEEPAK.P
Question ? Timing Diagram LDA DEEPAK.P
Review; Machine Cycles DEEPAK.P
MEMORY INTERFACING 30/7/14 DEEPAK.P 119
Memory and I/O addressing DEEPAK.P
Memory There are several different types of memory in a 8085 micro. One is Program memory. This is where the program is located. RAM Another is Data memory. This is where data, that might be used by the program, is located. DEEPAK.P
memory DEEPAK.P
memory ROM DEEPAK.P
memory DEEPAK.P
memory Some of the RAM IC's are given as: 1. IC 2114 -> 1k x 4bits 2. IC 6116 -> 2k x 8bits 3. IC 6264 -> 8k x 8bits Some of the ROM IC's are given as: 1. IC 2708 -> 1k x 8bits 2. IC 2716 -> 2k x 8bits 3. IC 2732 -> 4k x 8bits 4. IC 2764 -> 8k x 8bits 5. IC 27128 -> 16k x 8bits 6. IC 27256 -> 32k x 8bits 7. IC 2708 -> 64k x 8bits DEEPAK.P
Memory addressing or Mapping DEEPAK.P
Memory addressing or Mapping DEEPAK.P
Memory addressing or Mapping DEEPAK.P
Memory addressing or Mapping DEEPAK.P
Memory interfacing DEEPAK.P
Memory interfacing 64KB DEEPAK.P
Memory interfacing 64KB In this system the entire 16 address lines of the processor are connected to address input pins of memory IC. The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground). Since the processor is connected to EPROM, the active low RD pin is connected to active low output enable pin of EPROM. The range of address for EPROM is 0000H to FFFFH. DEEPAK.P
Multiple Memory interfacing DEEPAK.P
Two 32 kb Memory interfacing DEEPAK.P
Two 32 kb Memory interfacing Implement 32kb memory capacity of EPROM using single IC 27256. 32kb RAM capacity is implemented using single IC 62256. The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the processor are connected to 15 address pins of both EPROM and RAM. DEEPAK.P
Two 32 kb Memory interfacing The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If A15 is 0, it select EPROM. The memory used is both Ram and EPROM, so the low RD and WR pins of processor are connected to low WE and OE pins of memory respectively. The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 7FFFH to FFFFH. DEEPAK.P
Multiple Memory interfacing DEEPAK.P
32kb Memory interfacing using 4 “8 kb” DEEPAK.P
32kb Memory interfacing using 4 “8 kb” The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM. Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are connected to 13 address pins of all the memory. The address lines and A13 - A14 can be decoded using a 2- to-4 decoder to generate four chip select signals. DEEPAK.P
64kb Memory interfacing using 4 “8 kb” These four chip select signals can be used to select one of the four memory IC at any one time. The address line A15 is used as enable for decoder. DEEPAK.P
Multiple Memory interfacing DEEPAK.P
Memory Decoder DEEPAK.P
Multiple Memory interfacing DEEPAK.P
I/O INTERFACING 30/7/14 DEEPAK.P 144
I/O addressing or Mapping DEEPAK.P
I/O devices DEEPAK.P
I/O devices DEEPAK.P
I/O Interfacing DEEPAK.P
I/O Addressing Schemes DEEPAK.P
Memory Mapped I/O addressing DEEPAK.P
I/O Mapped I/O addressing DEEPAK.P
I/O Mapped I/O addressing DEEPAK.P
I/O Mapped I/O addressing DEEPAK.P