January, 2003CMS Ecal1 MGPA Specification Discussion – 9 th Jan. 03 OUTLINE 3 or 4 gain channels discussion technical background - why 3 gains could be preferred? simulation comparisons of 3 and 4 channel versions – effect of process variations implications for layout summary possible CAL circuit (very brief): proposed circuit and simulation result

January, 2003CMS Ecal2 Noise ( C IN v FET 2 v Rpf 2 R pf 1 charge amp. stage s.f. RGRG 4 diff. O/P gain stages C pf V CM CICI RIRI 4 transconductance (VI) gain stages i CFET 2 i RG 2 Original design 4 channel version all diff. O/P stages identical different gains implemented by values of RG Main noise sources: Rpf, VFET, gain resistor (RG) and VI FET relative importance depends on channel gain -> value of RG for low gain ranges RG large, noise becomes unacceptably large proposed solution: keep RG small and vary diff O/P stage gain

January, 2003CMS Ecal3 Re-distributing gains between diff O/P and RG to keep RG small RGRG diff O/P gainOverall gain RGRG diff O/P gain chan previous 4 chan now gain re-arrangement not completely trivial need to compensate pulse shape variations for different gains due to different parasitics in O/P circuit not needed when all O/P stages identical

January, 2003CMS Ecal4 Diff O/P stage gain compensation O/P termination defines dominant time constant inherent high frequency bandwidth determined by input resistance and capacitance -> parasitic (short) time constant (few nsec) depends on W/L ratios and drain currents but gain also depends on W/L ratios and currents -> different gain channels have different parasitic time constants can compensate by adding extra internal capacitance works OK but process variations affect W/L ratios (effective length varies) => external termination capacitance needs tuning to compensate for internal variations can be done but leads to different termination capacitors for different channels 2.5 pF/ns

January, 2003CMS Ecal5 Any way to improve? -> make use of FPPA spec review (“Memo on FPPA specifications”, C.Seez (August, 2002)) -> conclusions: 1. not possible to relax 60 pC full range signal 2. three gain ranges adequate for barrel 0 – 140instead of 0 – 50 note: highest gain required 140 – – 200 reduced by factor ~3 300 – 1250 GeV – three gain ranges also acceptable for endcap

January, 2003CMS Ecal6 Possible improvements from going to 3 gains using FPPA spec review conclusions can re-instate equal diff O/P gains, since highest gain can be reduced Overall gain RGRG diff O/P gain 32~ ~402 1~801 Overall gain RGRG diff O/P gain Gain range (barrel) [GeV] ~10~20~ ~5~40~ ~1~200~ – chan version 3 – chan version implications channel to channel pulse shape variation dependence on process spread goes (matching guaranteed by design) no internal compensation required & no process dependent external component selection R = 200  -> slightly increased noise for lowest gain range; 28,000 -> 34,000 electrons noise performance for other 2 ranges remains < 10,000 electrons (7000 – 8000)

January, 2003CMS Ecal7 Simulated pulse shape (4 gain channel version) results here for nominal process parameters:  = 0 ½ fullscale signals shown for each gain range use gain matching spec. to compare (Vpk-25ns)/Vpk should match to 1% highest:-0.2% higher:+0.2% lower:+0.2% lowest:-0.2% note: sigma (continuous variable +ve & –ve) selects process variation (  L,VT) from distribution specified by manufacturer. Vpk Vpk-25ns Signal sizes highest gain channel: 1 pC higher: 4 pC lower: 8 pC lowest gain channel: 32 pC  = 0

January, 2003CMS Ecal8  = -1.5 highest:-1.7% higher:+0.5% lower:+0.5% lowest:+0.7% Pulse shape 4 chan. gain version,  = -1.5 highest gain pulse shape (solid line) rise time now too slow => need to tune diff O/P stage external termination components to speed up (reduce Cdiff) can be done (precision 0402 capacitors available) Vcm Cdiff

January, 2003CMS Ecal9 process parameter variation pulse shape example (4 gain channel version) (without any external compensation)  = -1.5  = 0  = +1.5 highest: 1 pC higher: 4 pC lower: 8 pC lowest: 32 pC highest:-1.7% higher:+0.5% lower:+0.5% lowest:+0.7% highest:-0.2% higher:+0.2% lower:+0.2% lowest:-0.2% highest:+0.7% higher:-0.03% lower:-0.03% lowest:-0.6% Pulse Shape Matching

January, 2003CMS Ecal10 3 gain channel version - no external compensation necessary because diff O/P stage parasitics same for all 3 chans  = -1.5  = 0  = +1.5 highest: 3 pC middle: 6 pC lowest: 30 pC highest:-0.04% middle:-0.04% lowest:+0.08% Pulse Shape Matching highest:-0.3% middle:-0.2% lowest:+0.5% highest:0% middle:0% lowest:0%

January, 2003CMS Ecal11 4 channel 3 channel Layout benefits of 4 -> 3 channels 80 pin packages

January, 2003CMS Ecal12 Noise justification for gain of 32? barrel: 1250 GeV -> 60 pC highest gain range3210 fullscale signal40 Gev (2pC)125 GeV (6 pC) least significant bit10 MeV31 MeV digitisation noise (root 12)2.9 MeV8.9 MeV + 40 MeV electronic noise40.1 MeV41 MeV

January, 2003CMS Ecal13 Summary (1) original 4 channel design worked well from pulse shape matching viewpoint different gains realised by different RG values in VI stage -> all diff O/P gains identical but low gain channel noise too high redistributing gains between RG and diff O/P stage solves noise problem pulse shapes for different gain channels matched by internal compensation but process variations give effects which can only be compensated by selecting slightly different output termination capacitors for different gain channels difficult to quantify how big a problem but likely to complicate production e.g. production testing, VFE module assembly (won’t have standard set of component values)

January, 2003CMS Ecal14 Summary (2) benefit of 4 -> 3 channels pulse shape matches inherently (by design): no need to “tune” pulse shape to cope with process spread by selecting different O/P termination capacitance (now checked for wide range of parameter variations (np mismatch, supply voltage, temp.) layout: minimum pin count reduced – can use more power pins (will need some extra pins for CAL circuit and I2C test) power: ~ 600 mW - > ~500 mW simplistic conclusion (from electronics perspective only) 3 gain channels -> all diff O/P stages identical -> more robust design -> less risk (note: all previous talks can be found at:

January, 2003CMS Ecal15 Possible simple CAL circuit can adjust resistor values to get 2 or 3 points per MGPA gain range requires external trigger (where from?) On-chip Off-chip

January, 2003CMS Ecal16 CAL circuit simulation 10pF 1nF DAC value e.g. 100mV MGPA I/P 10k Rtc Rtc:0 ->10  Highest gain channel O/P for 1 pC input signal Can use Rtc to simulate real signal risetime external components