Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Applied VLSI Course and contest Results of Phase 3 Hani Samara 1

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Some improvments on the last Design: Ripple Carry Adder CSA with CLA Multiplier still the same one: Array Multiplier CSA CLA Sum 2

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Design factors for ASICs Max Freq. : 250 … 500 MHz Leackage Power: 1.0 … 4.7 uW Supply Voltage: 1.0 – 2.0 V Optimization : Area, Speed, and leakage Power Result: Increase the Voltage more Leakage Power but faster design 3

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock 4 Leakage Power vs. Supply Voltage

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Synthesis results: Mandatory values for ASIC Frequency250 MHz P_leackage uW E_avg N_cycles41374 Metric4.768 pJ 5

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! 6