Zvi Kohavi and Niraj K. Jha 1 Testing of Combinational Circuits

2 Fault Models Defects -> Faults -> Errors -> Failures Fault models: modeling of multiple defects as single faults at a higher level of abstraction Significantly reduces test derivation burden Faults may change internal logic values or voltage/current levels or the temporal behavior of the circuit Most common levels of fault abstraction: structural and switch-level Structural fault models: these ensure that the interconnections in a given circuit structure are fault-free and able to carry both 0 and 1 signals Stuck-at fault model: a line is stuck-at 0 (s-a-0) or stuck-at 1 (s-a-1) if it remains fixed at a low or high voltage, respectively, assuming positive logic –The most successful fault model in IC history

3 Stuck-at Fault Model A stuck-at fault does not necessarily imply that the line is shorted to ground or power supply It may model many cuts or shorts internal or external to a logic gate E.g., a cut on the stem of a fanout may result in a s-a-0 fault on all its fanout branches –However, a cut on just one fanout branch may result in a s-a-0 fault on just that fanout branch –Hence, stuck-at faults on fanout stems and branches have to be considered separately Types of stuck-at faults: Single: occurs on only one line of the circuit Multiple: simultaneously occurs on many lines A circuit with k lines: has 2k single stuck-at faults, but 3 k -1 multiple stuck- at faults Thus, explicitly targeting multiple stuck-at faults is impractical

4 Stuck-at Fault Model (Contd.) Example: Consider above circuit To test for c 1 s-a-0: one possible test vector is (1,1,0,1) Multiple (c 1 s-a-0, c 2 s-a-0, x 3 s-a-1) fault: also detected by (1,1,0,1) Stuck-at fault model also useful for future nanotechnologies: e.g., RTD- HFET based MOBILEs

5 Switch-level Fault Models Switch-level fault models: deal with faults in transistors and interconnects in switch-level description of the circuit Stuck-open fault model: refers to a permanently non-conducting transistor Example: Defect d 1 causes a stuck-open fault Exhaustive testing not enough: Test sequence {(0,0), (0,1), (1,0), (1,1)} does not give any error and hence does not detect d 1 Two-pattern tests needed to detect d 1 : {(0,0), (1,0)} –Initialization vector: (0,0) –Test vector: (1,0) Test sequence to detect all four stuck-open faults: {(0,0), (0,1), (0,0), (1,0)}

6 Stuck-on Fault Model Stuck-on fault model: refers to a permanently conducting transistor Example: defect d 2 causes a stuck-on fault Vector (1,1): in the presence of d 2, Q 1, Q 2, and Q 4 conduct, resulting in some intermediate value at the output –If this maps to value 1 at the output: the fault is detected, else not Now suppose, a stuck-on fault in Q 2 is present: only possible test is (1,0) –In the presence of this fault: again Q 1, Q 2, and Q 4 conduct –This time, we need value 0 at the output for detection Thus, by monitoring the output logic values: only one of these faults will be detected I DDQ testing needed: measures the current drawn

7 The Bridging Fault Model Bridging faults: shorts between interconnects BF: For some vectors, conducting path from V dd to V ss created: (1,1,0), (0,0,1), (0,1,1), (1,0,1) These vectors cause opposite logic values on c 1 and c 2 in the fault-free case: an intermediate voltage in the presence of the fault I DDQ testing needed Types of BFs: feedback and non-feedback

8 Delay Fault Models Delay faults: adversely impact the signal propagation delays, causing an incorrect value to be latched at the output Transition faults: defined for a logic gate whose output has a lumped delay fault that delays its 0 -> 1 or 1 -> 0 transition by more than the system clock period Path delay faults: when a path from a primary input to a circuit output is slow to propagate a 0 -> 1 or 1 -> 0 transition Path delay fault model more general of the two: models the cumulative effect of delay variations of gates and wires along the path –However, because the number of paths in a circuit can be very large: it takes much more time to generate and apply tests Two-pattern tests needed: because of the need to propagate transitions

9 Delay Fault Models (Contd.) Example: In the circuit below Path shown in bold: may have a path delay fault Consider G 3 : if a 0 -> 1 (1 -> 0) transition through every path going through G 3 is significantly delayed, then G 3 is said to have a slow-to-rise (slow-to-fall) transition fault

10 Structural Testing Structural testing: detection of faults on the interconnects in the circuit structure Test generation time: the time it takes to generate a test set for the targeted faults on a computer Test application time: the time it takes to apply the test vectors to the circuit under test Fault coverage: percentage of all targeted faults that are actually detected by the derived test set

11 Path Sensitization Path sensitization: activating a path through the fault site from the primary inputs to a circuit output in order to detect the fault Example: Sensitized path to detect A s-a-1 Other faults also detected: s-a-0 at m, n, and p and s-a-1 at q A s-a-0 detected by complementary values on the sensitized path One-dimensional path sensitization: the above two vectors detect all single stuck-at faults along the path Fault activation: at the fault site, assign a value complementary to the fault Error propagation: Sensitize a path from the primary inputs to a circuit output through the fault site Line justification or consistency: determine the primary input values that produce all the necessary signal values specified in above two steps

12 Path Sensitization (Contd.) Example: test for c 1 s-a-1 Assign 0 to c 1 Choose a path to be sensitized: through G 5, G 7, and G 9 –Make side-inputs of G 5 and G 9 0 Justify 0’s at lines c 2 and c 7 at the primary inputs –To make c 7 = 0: x 3 = x 4 = 0 –To make c 2 = 0: (x 1,x 2 ) = (0,0) or (0,1) or (1,0) –To make c 1 = 0: x 5 = 1 Thus, test vector: (0,0,0,0,1) Other faults detected: c 3 or c 5 s-a-1, c 6 or f 2 or x 5 s-a-0

13 Implication Implication: given the logic value on some line, determine the logic values uniquely implied at other lines Backward and forward Example: Implication of c 7 = 0 Backward: x 3 = c 4 = 0 Forward: f 1 = 0 Backtrack: Various path sensitization choices may exist: (G 4,G 6,G 9 ), (G 4,G 6,G 8 ) When one choice leads to a conflict: backtrack and choose another path

14 Fault Collapsing Fault collapsing: reduction of the list of faults that needs to be targeted without giving up fault coverage Redundant (or untestable) fault: fault-free and faulty truth tables are identical Fully testable (or irredundant) circuits: in which all single stuck-at faults are testable Fault equivalence: two faults are equivalent if their truth tables are identical For an n-input primitive gate: n+1 stuck-at faults are equivalent –All s-a-0 faults at the inputs and output of an AND gate –All s-a-1 faults at the inputs and output of an OR gate –All s-a-0 faults at the inputs and s-a-1 fault at the output of a NAND gate –All s-a-1 faults at the inputs and s-a-0 fault at the output of a NOR gate

15 Fault Collapsing (Contd.) Equivalence fault collapsing: reduces 2n+2 single stuck-at faults to n+2 AND gate: n+1 s-a-1 faults and any s-a-0 fault on the n+1 lines Fault dominance: Fault x dominates fault y if the set of all vectors that detect x is a superset of the set of all vectors that detect y Dominance fault collapsing: removal of the dominating fault from the fault list AND gate with inputs a, b, and output f: T f/1 = {(0,0), (0,1), (1,0)}, T a/1 = {(0,1)} and T b/1 = {(1,0)} Thus, f s-a-1 dominates a s-a-1 or b s-a-1 Dominance fault collapsing reduces the fault list to size n+1 for an n-input gate

16 Fault Collapsing Theorem Theorem 1: A test set that detects all single stuck-at faults at all primary inputs and fanout branches of an irredundant combinational circuit detects all single stuck-at faults in it Primary inputs and fanout branches: checkpoints Corollary: A test set that detects all single stuck-at faults at all primary inputs of a fanout-free combinational circuit detects all single stuck-at faults in it Example: Checkpoints: x 1, x 2, x 3, x 4, c 1, c 2, c 4, c 5 No. of faults reduces from 24 to 16 Further reduction: –x 1 s-a-0 and c 1 s-a-0 equivalent: remove one –x 3 s-a-0 and c 2 s-a-0 equivalent: remove one –x 4 s-a-0 and c 5 s-a-0 equivalent: remove one –c 4 s-a-0 equivalent to c 3 s-a-0 which dominates x 1 s-a-1 and c 1 s-a-1: remove c 4 s-a-0 –No. of faults further reduced from 16 to 12

17 D-algorithm D-algorithm: generalization of the one-dimensional path sensitization Can simultaneously sensitize multiple paths when necessary Error symbol D: composite value that represents a 1 on a line in the fault- free circuit and 0 in the faulty circuit D’: denotes the complementary situation Five-valued algebra: {0,1,,D,D’} D and D’ behave like any Boolean variable: –D + 0 = D, DD’ = 0, D + D’ = 1, DD = D + D = D, etc. Singular cover: compacted truth table Rows: singular cubes Propagation D-cubes: minimal conditions for error propagation through a gate

18 D-intersection D-intersection: process of combining different cubes using following rules D-intersection of cubes C 1 and C 2 : –Same value in each position where C 1 and C 2 have identical values –If the value is unknown in one cube: it denotes the value of the other cube in that position –If C 1 and C 2 have known, but different, values in any position: their intersection is null, i.e., leads to a conflict Example: Let C 1 = 0 1 D, C 2 = 1 D’ D, and C 3 = 0 0 D’ 1 C 1 C 2 = 0 1 D’ D C 1 C 3 = null

19 Primitive D-cube of a Fault (PDCF) and Test Cube PDCF: minimal condition for fault detection Example: for a NAND gate 1 1 D’ is a PDCF for output f s-a-1 0 D and 0 D are PDCFs for f s-a-0 Test cube: collection of all circuit signals set to a particular value from the five-valued algebra in order to derive a test vector

20 D-algorithm Steps 1.PDCF selection: select a PDCF for the targeted fault as the initial test cube and place the gate output with D or D’ on the D-frontier 2.Implication: perform backward and forward implication of the values assigned in Step 1. In case of conflict, backtrack 3.D-drive: intersect current test cube with a propagation D-cube of a gate whose input is on the D-frontier. Backtrack when necessary 4.Implication of D-drive: perform implication of the values assigned in Step 3. Repeat D-drive and its implication until an error signal reaches a circuit output 5.Line justification: For any gate G whose output is specified as 1 or 0, but inputs are not yet justified, perform line justification by intersecting the current test cube with a singular test cube of G 6.Implication of line justification: perform implication of the values assigned in Step 5. Repeat line justification and its implication until all specified values have been justified. Backtrack as necessary

21 D-algorithm Example Example: derive a test vector for the s-a-0 fault shown

22 I DDQ Testing I DDQ testing: detection of faults through supply current monitoring Specially suited to CMOS where quiescent supply current is normally low Error effects no longer have to be propagated to circuit outputs –Faults just have to be activated Test generation for bridging faults (BFs): target BFs between two nodes only Since, even if a BF involves multiple nodes, activating a BF between any two of these nodes will activate a path from V dd to V ss In absence of layout information: consider all two-node BFs When layout given: consider two-node BFs on adjacent nodes only Conditions for detecting BFs: let P(r) denote the value of node r on application of P to the fault-free circuit To detect non-feedback BF : P(r 1 ) and P(r 2 ) must have opposite values –This is an optimistic condition for detecting a feedback BF

23 Fault Collapsing: First Method 1.Suppose for every input vector P: P(r 1 ) = P(r 2 ) Then is redundant 2.If set of vectors T detects BFs between r 1 and nodes in set R: Then T will also detect the BFs between r 2 and nodes in R Hence, every BF involving r 2 can be replaced with a corresponding BF involving r 1 Example: Node c 1 is the root of a tree of inverters and buffers Since P(c 1 ) = P(c 4 ) = P(c 5 ) = P(c 6 ) and P(c 2 ) = P(c 3 ) for every P: –Just consider and ignore BFs involving nodes c 3, c 4, c 5, c 6 among themselves and with other nodes

24 Fault Collapsing: Second Method Consider a set of nodes S s.t. each node in S has the same fanin nodes and realizes the same function: Then a BF between any pair of nodes in S is redundant Example: condition satisfied for f 1 and f 2 Thus, only BFs involving either f 1 or f 2, but not both, need to be targeted Similarly, BFs involving internal nodes of either G 1 or G 2, but not both, need to be targeted

25 Test Generation for BFs Test generation: using a stuck-at fault test generator on a transformed circuit For, where c 1 and c 2 are gate outputs: insert an EXCLUSIVE-OR gate G with inputs c 1 and c 2 –Target stuck-at fault: s-a-0 at the output of G For involving two internal nodes of a gate: place opposite values on c 1 and c 2

26 Test Generation Example Example: For the BF shown: c 3 = 0 and c 5 = 1: –(c 1 = 1) and (x 4 = x 5 = 0): gate G 1 c 3 = 1 and c 5 = 0: –(x 1 = 1, c 1 = 0) and (x 4 = 1 or x 5 = 1): gate G 2 Target: s-a-0 fault at the output of G

27 Delay Fault Testing Underlying assumption: gate propagation delays are fixed and independent of input values Not entirely accurate: but suffices and keeps test generation tractable Clocking schemes: variable clock or rated clock Variable clock: test generation easier, test application more difficult Rated clock: test generation more difficult, test application easier

28 Basic Definitions Controlling input value: uniquely determines output value independent of other input values Else, non-controlling value Example: controlling value for OR or NOR: 1 controlling value for AND or NAND: 0 Path R: sequence g 0 g 1 …g r, where g 0 is a primary input, g 1 g 2 …g r-1 are gate outputs, and g r is a circuit output On-input of R: connection between two gates along R Side-input of R: any connection to a gate along R other than its on-input Two path delay faults (or logical paths): for each physical path R depending on the direction of signal transition along R If desired transition at g 0 is rising (falling): R ( R) Alternatively, if desired transition at g r is rising (falling): R (R )

29 Classification of Path Delay Faults Two main types of path delay faults: non-robustly testable and robustly testable (P 1,P 2 ) is a non-robust test: if and only if It launches the desired logic transition at the primary input of the path, and All side-inputs of the path settle to non-controlling values under P 2 Example: Application of {(0,1),(1,1)} Non-robust test for: x 1 c 1 c 2 f Cannot guarantee detection: if observation point is t 2, this test is invalidated since correct value 0 obtained for the second vector even in the presence of the fault –Can happen if fault x 1 c 2 f is also present

30 Robust Test A robust test can detect the targeted fault independently of the delays in the rest of the circuit: it must satisfy The conditions for non-robust tests, and Whenever the logic transition at an on-input is from a non-controlling value to a controlling value, each corresponding side-input should maintain a steady non-controlling value Example: Application of {(0,0),(1,0)} Robust test for: x 1 c 2 f

31 Validatable Non-robust Test A non-robust test may be invalidated by other path delay faults: however, if the invalidating path delay faults are robustly testable, then the non-robust test is called validatable Example: the rising transition at f just after t 2 corresponds to x 1 c 2 f, which has a robust test {(0,0),(1,0)} If the circuit passed this test: then the observation time can only be t 3 or t 4 when {(0,1),(1,1)} is applied In both cases: the test is valid Thus, {(0,1),(1,1)} is a validatable non-robust test for x 1 c 1 c 2 f –Because either the path delay fault is caught if the observation time is t 3 or the circuit is free of this fault if the observation time is t 4

32 Test Generation for Path Delay Faults Five-valued system and covering relationship:

33 Implication Tables

34 Test Generation for Robustly Testable PDFs In deriving two-pattern tests for PDFs: U0 and U1 are interpreted in two different ways U0 (U1) on an on-input is interpreted as a 1->0 (0->1) transition U0 and U1 on other lines have the conventional interpretation: signals with final value 0 (1) (P 1,P 2 ) robustly tests a PDF if and only if: It launches the desired transition at the input of the path, and The side-inputs have values covered by the following table –Such side-inputs are called robust Example: Robust side-inputs

35 Robust Test Generation Example Example: Suppose the bold path with a rising transition at its input needs to be tested Two-pattern test: {(0,,0,0, ), (0,,1,0,0)}

36 Test Generation for Non-robustly Testable PDFs Relax conditions as follows: Example: Non-robust side-inputs A non-robustly testable PDF has at least one non-robust side-input To reduce the chance of test invalidation: reduce the number of non- robust side-inputs Slack: the amount of time by which the non-controlling value on the side- input becomes stable before the on-input becomes stable If slacks of all side-inputs are positive: no test invalidation can occur Aim of test generation: maximize the slack of non-robust side-inputs

37 Making Non-robust Tests Validatable Make non-robust tests with minimal number of non-robust side-inputs and maximal slack validatable when possible: If two-pattern test P has don’t cares: specify them to minimize the number of transitions at the primary input –E.g., specify U1 as 11 –Specify U0 as 00 –Specify XX as 00 or 11 After P new is obtained this way: check for the non-robust side-inputs that need to be robustly tested to validate P new –If these identified logical paths are indeed robustly testable: then the non-robust P new is validatable

38 Test Generation for Transition Faults (P 1,P 2 ) is a slow-to-rise transition test at output g i of some gate in a circuit if it satisfies: g i (P 1 ) = 0, and g i (P 2 ) = 1 and a path is sensitized from g i to some circuit output under P 2 –Thus, P 2 is simply a s-a-0 test for g i (P 1,P 2 ) is a slow-to-fall transition test at output g i if: g i (P 1 ) = 1, and P 2 is a s-a-1 test for g i To reduce the possibility of test invalidation: choose P 1 and P 2 that differ in only one bit whenever possible

39 Transition Fault Testing Example Example: Test for a slow-to-rise transition fault at c 3 P 1 must make c 3 = 0: (,,0,, ) P 2 must make c 3 =1 and sensitize any path from c 3 to f: (0,,1,1,1) A possible two-pattern test: {(0,0,0,1,1), (0,0,1,1,1)}

40 At-speed Test Generation At-speed tests: rated clock tests Under the assumption that the delay fault (either PDF or TF) does not cause the delay of the path to exceed two clock cycles: A variable clock two-pattern test (P 1,P 2 ) can be converted to: a rated clock three-pattern test (P 1,P 1,P 2 ) –Signal values are guaranteed to stabilize when the first vector is left unchanged for two clock cycles Generalization: under the assumption that the delay fault does not cause the delay of the path to exceed n clock cycles: Derive an (n+1)-pattern test: where P 1 is replicated n times

41 Synthesis for Testability Incorporate testability considerations: during synthesis itself Synthesis for full testability: remove all redundancies from the circuit s.t. it becomes fully testable Synthesis for easy testability: aimed at reducing test generation and applications times and increasing fault coverage Synthesis of two-level circuits for stuck-at fault testability: Two-level circuits: frequently the starting point for further logic optimization An AND-OR or NAND-NAND circuit based on an irredundant sum of products: fully testable for all single stuck-at faults A single stuck-at fault test set: also detects all multiple stuck-at faults in the circuit The same results hold: for an OR-AND or NOR-NOR two-level circuit derived from an irredundant product of sums Example: Two-level circuit for f = x 1 x 2 + x 2 x 3 {(0,1,0), (0,1,1), (1,0,1), (1,1,0)} detects all single stuck-at faults in it (hence, also all multiple stuck-at faults)

42 Transformations to Preserve Single Stuck-at Fault Testability Logic transformations: to convert an initial single stuck-at fault testable circuit to a final circuit which is also single stuck-at fault testable Algebraic divisor: single-cube or multiple-cube Example: For f = x 1 x 2 x 3 + x 1 x 2 x 4 + x 5 g 1 = x 1 x 2 is a single-cube algebraic divisor g 2 = x 2 x 3 + x 2 x 4 is a multiple-cube algebraic divisor If we express f as x 1 g 2 + x 5 : g 2 is said to be algebraically resubstituted in f By identifying algebraic divisors common to two or more expressions and resubstituting them: can convert a two-level circuit into a multi-level circuit (see Chapter 6) Complements of the divisors can also be resubstituted

43 Definitions A Boolean expression is cube-free: if the only cube dividing f evenly is 1 A cube-free expression must have more than one cube Example: x 1 x 2 + x 3 is cube-free, but x 1 x 2 + x 1 x 3 and x 1 x 2 x 3 are not Double-cube divisor: cube-free multiple-cube divisor having exactly two cubes Example: For f = x 1 x 4 + x 2 x 4 + x 3 x 4 Double-cube divisors: {x 1 + x 2, x 1 + x 3, x 2 + x 3 }

44 Methodology Obtain multi-level circuit using only: single-cube divisors, double-cube divisors, and their complements Complements obtained using: only De Morgan’s theorem Boolean reductions: (a + a = a; a + a’ = 1; a.a = a; a.a’ = 0) not used Furthermore, for simplicity: use only two-literal single-cube divisors and double-cube divisors with at most two literals in each of the two cubes and at most three variables Single-cube extraction: extract cubes common to two or more cubes Create the common part as an intermediate node Example: From f = x 1 x 2 A 1 + x 1 x 2 A 2 + … + x 1 x 2 A n Extract cube C = x 1 x 2 Substitute to obtain CA 1 + CA 2 + … + CA n

45 Methodology (Contd.) Double-cube extraction: extract a double-cube from a single-output sum-of- products expression AC + BC to obtain C(A+B) Dual expression extraction: transform a sum-of-products expression f as follows: f = x 1 A 1 + x 2 A 1 + x 1 ’x 2 ’A 2 to M = x 1 + x 2 and f = MA 1 + M’A 2 f = x 1 x 2 ’A 1 + x 1 ’x 2 A 1 + x 1 ’x 2 ’A 2 + x 1 x 2 A 2 to M = x 1 x 2 ’ + x 1 ’x 2 and f = MA 1 + M’A 2 f = x 1 x 2 A 1 + x 2 ’x 3 A 1 + x 1 ’x 2 A 2 + x 2 ’x 3 ’A 2 to M = x 1 x 2 + x 2 ’x 3 and f = MA 1 + M’A 2 At each step of the synthesis process: the method greedily selects and extracts a double-cube divisor jointly with its dual expression or a single-cube divisor that results in the greatest literal-count reduction If above transformations applied to a single-output irredundant sum of products: single stuck-at testability is preserved If circuit C 1 is transformed to circuit C 2 : single stuck-at test set of C 1 is guaranteed to detect all single stuck-at faults in C 2 –Such transformations called test set preserving

46 Transformations to Preserve Multiple Stuck-at Fault Testability If algebraic factorization without complement is applied to a single-output two-level circuit based on an irredundant sum of products: then the resultant multi-level circuit is testable for all multiple stuck-at faults using the single stuck-at fault test set of the two-level circuit Divisors need not be limited to single-cube and double-cube divisors Even though general algebraic factorization preserves multiple stuck-at testability: it does not preserve single stuck-at fault testability Because in a single stuck-at fault testable circuit, a multiple stuck-at fault may be redundant: after algebraic factorization, it may become single redundant stuck-at fault Example: If we replace G 1 and G 2 with a single gate, corresponding to factoring a single cube: s-a-0 or s-a-1 at the output of H is not testable

47 Redundancy Identification and Removal Unintentional redundancies: due to sub-optimal logic synthesis Negative impact: larger chip area and delay than necessary Detecting redundancies: computationally intensive Test generation algorithms declare a fault redundant: if they fail to generate a test vector for it Presence of a redundant fault may: –invalidate the test for another fault, or –make a detectable fault redundant, or –make a redundant fault detectable –Thus, not possible to remove all redundancies in a single pass Redundancy identification and removal methods: Indirect: byproduct of test generation; thus, computationally expensive Direct: can identify redundancies without the search process involved in test generation –Static: analyze circuit structure and perform value implications –Dynamic: work with indirect methods, without requiring test generation –Don’t-care based: functional extraction and logic minimization

48 Indirect Method If a complete test generation method fails to generate a test for k s-a-0 (s-a-1): then k can be connected to 0 (1) without changing the function implemented by the circuit Then reduce circuit by: –Simplifying gates connected to constant values –Replacing a single-input AND/OR (NAND/NOR) by a direct connection (inverter) –Deleting all gates that do not fan out to any circuit output Simplification rules: 1.If input s-a-0 of an AND (NAND) gate is redundant: remove gate and replace with 0 (1) 2.If input s-a-1 of an OR (NOR) gate is redundant: remove gate and replace with 1 (0) 3.If input s-a-1 of an AND (NAND) gate is redundant: remove input 4.If input s-a-0 of an OR (NOR) gate is redundant: remove input

49 Indirect Method (Contd.) Example: Redundant faults in circuit (a): s-a-0: x 1, x 3, c 1 s-a-1: x 1, x 3, c 1, c 2, c 3 If none of these faults present: c 4 s-a-1 detected by (1,0,1,1) –However, presence of x 1 s-a-0 makes c 4 s-a-1 redundant Targeting x 1 s-a-0 for removal: obtain circuit (b) in first pass Do test generation for all the faults again: find both x 2 s-a-1 faults to be redundant –Removing either one: makes the other one detectable –Targeting either: arrive at circuit (c) in the second pass

50 Interesting Use of Indirect Method Deliberately add redundancies to an irredundant circuit: to create yet more redundancies which, upon removal, yield a more optimized circuit Mandatory assignments: value assignments to some lines that must be satisfied by any test vector for the given fault Control assignments Observation assignments If these assignments are simultaneously satisfiable: then the fault is redundant Using this approach: add redundant connections (with or without inversions) to maximize redundancies elsewhere Target these other redundancies for removal

51 Indirect Method Example Example: Consider c 1 s-a-0 in circuit (a) (ignore dashed connection) Mandatory control assignment: c 1 = 1 Mandatory observation assignment: c 2 = 0 These assignments imply: x 1 ’ = 1, x 3 = 1, x 2 = 0 –These imply: c 3 = 1, c 4 = 0, f 2 = 1 Since c 3 = 1: with dashed connection – no effect of c 1 s-a-0 at f 1 Thus, c 1 s-a-0 becomes redundant Verify that adding the connection does not change the input/output behavior of the circuit: in order to test for s-a-0 on it –Mandatory control assignment: c 3 = 1 –Mandatory observation assignments: c 1 = 0, c 2 = 0 –Assignments not jointly satisfiable: thus, connection redundant After adding connection: simplify logic because c 1 s-a-0 is now redundant Of course, dashed connection no longer redundant

52 Static Direct Method Static methods are very fast, as they don’t need exhaustive search: However, they are not able to identify all redundancies Useful as a preprocessing step to an indirect method Use an illegal combination of values to identify redundancies: Suppose values v 1, v 2, and v 3 cannot simultaneously occur on lines c 1, c 2, and c 3 –Then faults for which this illegal combination is mandatory are redundant First find faults for which each condition is individually mandatory Sc i vj : denotes the set of faults that must have value v j on line c i for detection The faults requiring the above illegal combination for detection are in: Sc 1 v1 Sc 2 v2 Sc 3 v3 Use uncontrollability and unobservability analysis to find these faults

53 Uncontrollability and Unobservability Uncontrollability status 0 u (1 u ): line cannot be controlled to 0 (1) Propagation rules: uncontrollability status propagated forward and backward If a gate input cannot be set to its non-controlling value: then all other inputs become unobservable Unobservability status: can be propagated backward from gate output to all its inputs Marking of a fanout stem as unobservable: requires satisfaction of special conditions Redundant faults identified as those: that cannot be activated [s-a-0 (s-a-1) faults on lines with 1 u (0 u )] or propagated (both faults on unobservable lines)

54 Extension of Method Method can be extended based on arbitrary illegal value combinations: 1.Form a list L of all fanout stems and reconvergent inputs 2.For each line c in L, find implications of c = 0 u (1 u ) to determine all uncontrollable and unobservable lines: let F 0 (F 1 ) be the set of corresponding faults 3.The redundant faults are in the set F 0 F 1 : reason is that such faults simultaneously require c to be 0 and 1, which is not possible Example: For circuit (a), L = {x 1, x 2, c 6, c 7 } Target c 6 c 6 = 0 u does not imply uncontrollability or unobservability of any other line: F 0 = {c 6 s-a-1} c 6 = 1 u implies: x 3 = c 5 = c 1 = c 3 = x 1 = x 2 = c 2 = c 4 = c 7 = f = 1 u Since c 6 = 1 u (c 7 = 1 u ): error propagating to c 7 (c 6 ) due to any fault cannot propagate to f Hence, F 1 = {s-a-0 on c 6, x 3, c 5, c 1, c 3, x 1, x 2, c 2, c 4, c 7, f and s-a-1 on c 6, x 3, c 5, c 1, c 3, c 7, c 2, c 4 } Since F 0 F 1 = {c 6 s-a-1}: c 6 s-a-1 is redundant. This yields circuit (b)

55 Dynamic Direct Method Dynamic method: also does not require exhaustive search It requires a test generator to first identify a redundant fault Thereafter, such a method identifies additional redundant faults It can remove identified redundancies in just one pass of test generation –However, it cannot guarantee a single stuck-at fault testable circuit at the end of the process It also takes advantage of uncontrollability and unobservability analysis Region of a redundant fault: subcircuit that can be removed because of it Level of a gate: max. level of any gate fanin + 1 Assume primary inputs to be at level 0 When region of a redundant fault r 1 is contained within the region of another redundant fault r 2 : it is preferable to target r 2 first Target the faults at higher levels first in test generation

56 Dynamic Direct Method (Contd.) Once a redundant fault has been removed: we need to identify the newly created redundancies These are faults that would have been detectable had the removal not occurred Theorem: Let A be an output of a redundant region R and G be the gate fed by A. Let c be the controlling value and i the inversion of G (0 for a non-inverting gate and 1 for an inverting one). Assume that the combination consisting of c’ values on the remaining inputs of G and c i value on its output was feasible (legal) in the old circuit. Then this combination is illegal as a result of removal. Once an illegal combination of values is identified: Uncontrollability/unobservability analysis: can identify the newly created redundancies Note that the uncontrollability status can be propagated forward and backward everywhere except through gate G Of all the newly created redundancies: only the highest-level fault is removed

57 Dynamic Method Example Example: suppose in circuit (a), the test generator has identified x 1 s-a-0 as redundant Region R of this fault: just gate G 1 This region feeds gate G 2 : whose controlling value is 1 and inversion 0 Combination (c 2 = 0, c 3 = 1) was legal in the old circuit –However, once R is removed: this combination becomes illegal Translate illegal combination to: c 2 = 0 u, c 3 = 1 u 0 u on c 2 can be propagated backward: –S c2 0 = {s-a-1 on c 2, x 2, c 4 } 1 u on c 3 can be propagated forward: recognizing that the side-inputs of G 3 become unobservable –S c3 1 = {s-a-0 on c 3, f, c 4, x 4, and s-a-1 on c 4, x 4 } Since S c2 0 S c3 1 = {c 4 s-a-1}: c 4 s-a-1 is newly redundant After removing this fault: we directly obtain circuit (b) in one pass –Earlier indirect method required two passes

58 Don’t Care Based Direct Method A multi-level circuit consists of an interconnection of various logic blocks: Even if these blocks are individually irredundant: the multi-level circuit can still contain redundancies Satisfiability don’t care set: vectors that cannot be fed to embedded blocks Observability don’t care set: vectors for which the block output are not observable at the circuit output Use these sets to resynthesize the logic blocks: such that the multi-level circuit has fewer redundancies

59 Don’t Care Based Method (Contd.) Let the Boolean variable corresponding to node j, for j = 1, 2, …, p, of the multi-level circuit be f j and the logic representation of f j be F j Satisfiability don’t care set, DSAT, is common to all nodes: DSAT = DSAT j, for j = 1 to p DSAT j = f j F j DSAT j can be interpreted to mean that since f j = F j, condition f j F j is a don’t care Let the set of circuit outputs be PO: Observability don’t care set, DOBS j, for each node j: DOBS j = DOBS ij, for i in PO DOBS ij = [(F i ) fj (F i ) fj’ ]’ DOBS j corresponds to a set of values at the primary inputs under which all the circuit outputs are insensitive to value f j that node j takes on

60 Don’t Care Based Method Example Example: Even though each block in circuit (a) is individually redundant, the circuit can be checked to be redundant Since f 3 = f 1 f 2 x 1 ’x 4 ’ + x 1 x 3 : –DOBS 1 = [(f 2 x 1 ’x 4 ’ + x 1 x 3 ) (x 1 x 3 )]’ = f 2 ’ + x 1 + x 4 Hence, f 1 = x 1 x 2 + x 3 can be simplified to just x 3 : since x 1 is in DOBS 1, which includes x 1 x 2 in f 1 –Interpretation: x 1 x 2 term in f 1 is not observable at output f 3 Similarly, DOBS 2 = f 1 ’ + x 1 + x 4 –Hence, f 2 = x 4 + x 5 can be simplified to just x 5 since x 4 is in DOBS 2 Using simplified equations f 1 = x 3 and f 2 = x 5 : –DSAT 1 = f 1 x 3 ’ + f 1 ’x 3 and DSAT 2 = f 2 x 5 ’ + f 2 ’x 5 Hence, f 3 can be simplified w.r.t. the don’t cares in DSAT 1 + DSAT 2 –f 3 = f 1 f 2 x 4 ’ + x 1 x 3 since the consensus of x 1 x 3 and f 1 x 3 ’ is x 1 f 1 which simplifies f 1 f 2 x 1 ’x 4 ’ to f 1 f 2 x 4 ’

61 Synthesis for Delay Fault Testability Robustly path delay fault testable circuit: if robust two-pattern tests exist for every path delay fault in it Two-level circuits: use tautology checking A function is a tautology: if it is 1 for all input vectors Suppose we want to test a path starting with literal l going through AND gate G and the OR gate: –Both path delay faults through this literal are robustly testable: if and only if after making the side-inputs of G equal to 1, the output values of the remaining AND gates can be made 0 using some combination without using l or l’ –Thus, we can first make the side-inputs of G 1, delete l and l’ from the remaining products, and then delete G from the corresponding sum of products »If the remaining switching expression becomes a tautology: then the path is not robustly testable, else it is

62 Two-level Circuit Example Example: Circuit implements f = x 1 x 2 + x 1 x 3 ’ + x 1 ’x 3 Suppose we want to robustly test the rising transition shown in circuit (a) We first enable side-input x 2 = 1 We then delete G 1, literal x 1 from G 2 and x 1 ’ from G 3 –Thus obtaining f red = x 3 ’ + x 3 = 1 Since f red is a tautology, the path is not robustly testable –The partial assignment shown in circuit (a), which is required for robust testability, is not satisfiable Now suppose we want to robustly test the path shown in circuit (b) –After making x 1 = 1: we obtain f red = x 3 ’ which can be made 0 by making x 3 = 1 –Thus, robust two-pattern test: {(1,0,1), (1,1,1)}

63 Two-level Circuits (Contd.) Necessary condition for robust path delay fault testability: implementation should be based on an irredundant sum of products Unfortunately, not sufficient: as we just saw Robust testability for transition faults: verify that for both rising and falling transitions, at least one path through each gate is robustly testable Using an irredundant sum of products: neither necessary nor sufficient for transition fault testability Example: Circuit implements f 1 = x 1 + x 2 + x 1 ’x 2 ’x 3 Not an irredundant sum of products: yet the slow-to-rise and slow-to-fall transition faults at the output of both G 1 and G 2 are robustly testable Consider f 2 = x 1 x 3 + x 1 x 2 + x 1 ’x 2 ’ + x 3 x 4 + x 3 ’x 4 ’ –Even though it is irredundant: transition faults at the output of the first AND gate are not robustly testable since neither of the paths from x 1 and x 3 is robustly testable

64 Multi-level Circuits Shannon’s decomposition: can be used to obtain a robust path delay fault testable circuit which is also completely testable for all combinations of multiple stuck-at faults and stuck-open faults Shannon’s decomposition: f(x 1,x 2, …,x n ) = x i f xi + x i ’f xi’ If f is binate in x i : then the decomposed circuit is robustly testable if the subcircuits for the two cofactors are robustly testable If subcircuits are not robustly testable after one decomposition: apply decomposition recursively to the cofactors until robustly testable subcircuits are obtained –Guaranteed to terminate in n-2 steps: since that will yield a two- variable cofactor that is guaranteed to be robustly testable –One can also stop when a unate cofactor is obtained: also guaranteed to be robustly testable –Actually, most binate cofactors are robustly testable too

65 Shannon’s Decomposition (Contd.) Heuristic 1 for choosing the binate variable to target first for decomposition: choose the one that appears the most number of times in complemented or uncomplemented form in the sum of products Heuristic 2: choose a variable that leads to robust untestability in a maximum number of gates Example: Consider f 2 = x 1 x 3 + x 1 x 2 + x 1 ’x 2 ’ + x 3 x 4 + x 3 ’x 4 ’ Robustly untestable literals: x 1 and x 3 in the first AND gate Using either heuristic: we can choose either x 1 or x 3 Choosing x 1 : f 2 = x 1 (x 2 + x 3 + x 4 ’) + x 1 ’(x 2 ’ + x 3 x 4 + x 3 ’x 4 ’) Since the two cofactors are robustly testable: so is the decomposed circuit for f 2

66 Algebraic Factorization Given a robustly path delay fault testable circuit: algebraic factorization with a constrained use of complement maintains its robust path delay fault testability Robust test set is also preserved after factorization Main problem with the approach: frequently, two-level circuits based on irredundant sum of products, which are starting points for synthesis, are not robustly testable For f 1 = x 1 x 2 + x 1 x 3 ’ + x 1 ’x 3 : no irredundant sum of products leads to robust testability For f 2 = x 1 x 2 ’ + x 1 ’x 2 + x 1 x 3 ’ + x 1 ’x 3 : literal x 1 in x 1 x 2 ’ is not robustly testable –However, f 2 has another realization: x 1 x 2 ’ + x 1 ’x 3 + x 2 x 3 ’, which is robustly testable

67 Algebraic Factorization (Contd.) Heuristic: bias the two-level logic synthesizer towards robustly testable implementations, whenever possible Relatively essential vertex of a prime implicant in a sum of products: minterm that is not contained in any other prime implicant in the sum of products Heuristic tries to maximize the number of relatively essential vertices in the prime implicant: that are just one bit different from some vertex in the OFF-set of the function –Increases the probability of meeting the necessary and sufficient conditions for robust path delay fault testability

68 Algebraic Factorization (Contd.) Surprisingly, algebraic factorization does not main robust transition fault testability Example: Circuit (a) is robustly testable But after algebraic factorization: circuit (b) is not since no path through G 3 is robustly testable To preserve robust testability: use a constrained form of algebraic factorization –Each cube in each factor should have at least one path through it: which is robustly testable –Thus, if we had used x 1 ’x 3 or x 2 ’x 3 as a factor instead of x 1 ’x 2 ’: robust testability would have been maintained

69 Targeted Algebraic Factorization Useful in obtaining a robustly testable multi-level circuit in the vast majority of cases where the original two-level circuit is not robustly testable Main idea: First convert the two-level circuit, which is not robustly testable, into an intermediate circuit (typically, with three or four levels) which is Then algebraic factorization with a constrained use of complement can be used as before Consider the irredundant sum of products Suppose that –(a) in each term in f, all literals in M j are robustly testable –(b) each literal in set {x 1,x 2, …,x n } is robustly testable in at least one product term in f, and –(c) the other literals in f are not necessarily robustly testable Then literals x 1, x 2, …, x n are robustly testable when factored out:

70 Targeted Algebraic Factorization (Contd.) Example: Consider the irredundant sum of products f 1 = x 1 x 2 x 3 * + x 1 *x 3 x 4 + x 1 ’x 2 ’x 4 + x 3 ’x 4 ’, where starred literals are not robustly testable Using the synthesis rule: we obtain f 1 = x 1 x 3 (x 2 + x 4 ) + x 1 ’x 2 ’x 4 + x 3 ’x 4 ’, which is robustly testable Example: Consider f 2 = x 1 x 2 *M 1 + x 1 *x 2 M 2 + x 1 *x 2 *M 3 + x 1 *M 4 + N 1 Using synthesis rule once: f 2 = x 1 x 2 (M 1 + M 2 + M 3 ) + x 1 *M 4 + N 1 Using it again: f 2 = x 1 {x 2 (M 1 + M 2 + M 3 ) + M 4 } + N 1, where both x 1 and x 2 are now robustly testable When the synthesis rule is not successful with the sum of products for f: it is frequently successful with f’ Repeated Shannon’s decomposition is not area-efficient: whereas area- efficient algebraic factorization cannot guarantee robust testability Apply targeted algebraic factorization: when applicable, to Shannon cofactors

71 Test Generation for Nanotechnologies Test generation for a threshold gate that implements f(x 1,x 2, …,x n ): x i s-a-0: activated by x i = 1 In the fault-free case: –Moving w i to the RHS: When the fault is present:

72 Test Generation for Nanotechnologies (Contd.) A test vector can be found for x i s-a-0 by finding an assignment on the input variables with x i = 1: such that Eqs. (8-3) and (8-6) or Eqs. (8-4) or (8-5) are satisfied Similar analysis for x i s-a-1: now Eqs. (8-3) and (8-4) [(8-5) and (8-6)] refer to the faulty (fault-free) cases Theorem: To find test vectors for x i s-a-0 and x i s-a-1 in a threshold gate implementation of f(x 1,x 2, …,x n ), we must find an assignment of values to the remaining input variables such that one of the following inequalities is satisfied: If an assignment exists, then along with x i = 1 (x i = 0), it is a test vector. If an assignment does not exist, then both faults are redundant

73 Test Generation for Nanotechnologies (Contd.) Example: Consider a threshold gate that realizes f(x 1,x 2,x 3 ) = x 1 x 2 + x 1 x 3 with weight-threshold vector PDCF for x 1 s-a-0: 101D, 110D, 111D Propagation D-cubes: substituting D for x 1, we get Dx 2 + Dx 3 Thus, {D10D, D01D, D11D} and {D’10D’, D’01D’, D’11D’ } are propagation D-cubes

74 D-algorithm Example Example: Test for x 1 s-a-1 PDCF in gate G 1 : 0000D’ Error propagated using the propagation D-cube shown Justification of 1 needed on c 2 by applying the relevant singular cube to gate G 3

75 Redundancy Removal Fault-free threshold gate and its faulty representations: Example: redundancy removal for c 1 s-a-0 (s-a-1)