1 PD Loop Filter 1/N Ref VCO Phase- Locked Loop LO

2 Frequency Divider Design Example Yu Lin

3 Frequency Divider approaches(1) Analog approaches –Regenerative injection-locked frequency divider –Basic mixer theory: f o =f in -f LO –Examples If f o =f LO, then f in =2f o If third harmonic of LO, f LO =3*f o

4 Frequency Divider approaches(2) Digital logic approaches –Static Logic: bistable circuit as memory –Divider/2 Examples Edge-Triggered DFF. Input Output D CLK Input Output D CLK Q Q D

5 Eg 2. JK FF –J=K=1, toggle T H < (t ud1, t dd2 ) < T t ud1 t dd2 T THTH

6 Frequency Divider approaches(3) Digital logic approaches –Dynamic Logic –No dedicated bistable circuit –Parasitic cap between node as storage element –Compared to static approach Faster Simpler implementation Frequency has lower limit

7 Design of divide/2 –SiGe BiCMOS –Dynamic frequency divider –Input frequency: 40GHz –+/-20% input frequency range (32GHz~48GHz) –Work from 0  C to 100  C at 40GHz –Input 200mv –Output 200mV Reinhold, M.; Dorschky, C.; Rose, E.; Pullela, R.; Mayer, P.; Kunz, F.; Baeyens, Y.; Link, T.; Mattia, J.-P., A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology, Solid-State Circuits, IEEE Journal of Vol.36, Issue 12, Dec Page(s):

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9 0.5T< (t ud1, t dd2 ) < T t dd1 t ud2 T

10 Four-phase clock Fully differential 0  C or 90  C phase-shifted t dd1 t ud2 T

11 Design key points Find optimal current density for highest f t Choose appropriate current for the current sources Choose appropriate resistors to set up good quiescent points Appropriate resistance and parasitic capacitance, delay time (t dd1 and t ud2 ) around 0.75*T

12 Design key points(2) Resistances are related to the quiescent point and input frequency range, key point of robust design Added buffer to do level shifting, improve the driving capability and adjust gain Driving capability increases when increase the current

13 Simulation results(1) The output of divider core at 27°C with normal model with 28G Hz input

14 Simulation results(2) The output of divider core at 27°C with normal model with 40G Hz input

15 Simulation results(3) The output of divider core at 27°C with normal model with 53G Hz input

16 Simulation results(4) Frequency range (GHz) SlowNormalFast 0C0C  C  C

17 VCO Design Example Chao Su Chao Su; Thoka, S.; Kee-Chee Tiew; Geiger, R.L., A 40 GHz modified-Colpitts voltage controlled oscillator with increased tuning range, ISCAS '03. Proceedings of the 2003 International Symposium onVolume 1, May 2003 Page(s):I I-720 vol.1

18 A system with characteristic If It will oscillate at

19 Basic Colpitts VCO Oscillate when Assume for inductor Where Then

20 For given L, g m, C , –W ide frequency range can be obtained with high Q by tuning C L –High Q can be achieved with reduction of effective G P

21 Modified Colpitts Circuit Achieve negative resistance by cross- coupled BJT

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23 Simulation results

24 Divide/2Modified Colpitts VCO

25 Measurement Results Three VCOs with three different inductors f VCO =(28~31GHz) f d/2 =(14.8~16GHz) Tuning range smaller compared to simulation