© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2002

© Digital Integrated Circuits 2nd Inverter Power Dissipation

© Digital Integrated Circuits 2nd Inverter Where Does Power Go in CMOS?

© Digital Integrated Circuits 2nd Inverter A First-Order RC Network v out v dd CLCL R Only half of the energy supplied by the power source is stored on load. The other half is dissipated by the PMOS transistor. It is independent of size when load capacitor dominates!!!

© Digital Integrated Circuits 2nd Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd

© Digital Integrated Circuits 2nd Inverter Modification for Circuits with Reduced Swing

© Digital Integrated Circuits 2nd Inverter Node Transition Activity and Power Switching factor

© Digital Integrated Circuits 2nd Inverter Transistor Sizing for Minimum Energy (1)  Goal: Minimize Energy of whole circuit with  Design parameters: f and V DD  t p  t pref of circuit with f = 1 and V DD =V ref Minimizing energy without delay constraints is not meaningful C ext /C g1 =F

© Digital Integrated Circuits 2nd Inverter Transistor Sizing for energy (2)  Performance Constraint (when  =1)  Energy for single Transition (when  =1) Gate: C g1 Intrinsic: γC g1 Gate: f C g1 Intrinsic: f γ C g1

© Digital Integrated Circuits 2nd Inverter Transistor Sizing for energy (3) F = V DD = M (f), V TE =0.5V, V ref =2.5V E/E ref = f (f), V ref =2.5V, V DD = M (f) F =1 This plots what V DD can be if delay constraint is met This plots what energy ratio is if using V DD derived Every point here has the same delay for given F

© Digital Integrated Circuits 2nd Inverter  Device sizing together with V DD scaling is very effective to reduce power consumption  Over-sizing does not pay back in terms of both delay and power consumption (design for right speed, not maximum)  Optimal sizing for energy is smaller than the one for delay Transistor Sizing for energy (4)

© Digital Integrated Circuits 2nd Inverter Short Circuit Currents Peak current is directly proportional to sizes !!! The time duration when both devices on

© Digital Integrated Circuits 2nd Inverter How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, why? but can’t do this for cascade logic, since making the output rise/fall too large slows down the later gates and can cause short circuit current for those gates. (global picture is important!!!) Large load capacitance cause large rise time

© Digital Integrated Circuits 2nd Inverter Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

© Digital Integrated Circuits 2nd Inverter Static power consumption: Leakage Sub-threshold current one of most compelling issues in low-energy circuit design! N+ P-sub

© Digital Integrated Circuits 2nd Inverter Reverse-Biased Diode Leakage diode leakage caused by thermally generated carriers! JS = pA/  m2 at 25 deg C for 0.25  m CMOS! JS doubles for every 9 deg C! At 85 degrees, a commonly imposed upper bound for junction temperatures in commercial hardware products, the leakage current increase by a factor of 60 over the 25 deg. Vdd

© Digital Integrated Circuits 2nd Inverter Subthreshold Leakage Component

© Digital Integrated Circuits 2nd Inverter Principles for Power Reduction  Prime choice: Reduce voltage!  Recent years have seen an acceleration in supply voltage reduction  Design at very low voltages still open question (0.6 … 0.9 V by 201x?)  Reduce switching activity (very difficult!)  Reduce physical capacitance  Device Sizing: for F=20 –f opt (energy)=3.5, f opt (performance)=4

© Digital Integrated Circuits 2nd Inverter Performance measure of inverter  Total power consumption  Power-delay product PDP gives a measure of energy, as from the units (w*s=Joule). Assuming inverter operating at its maximum switching frequency  Energy-delay product ( misconception about V DD in PDP ) A more relevant metric showing tradeoff between power and performance (delay) parameter

© Digital Integrated Circuits 2nd Inverter

© Digital Integrated Circuits 2nd Inverter Impact of Technology Scaling 10μm to 23nm

© Digital Integrated Circuits 2nd Inverter Goals of Technology Scaling  Make things cheaper:  Want to sell more functions (transistors) per chip for the same money  Build same products cheaper, sell the same part for less money  Price of a transistor is reduced ?  But also want to be faster, smaller, lower power, lighter  Reduce gate delay  Increase transistor density  Reduce energy per transition

© Digital Integrated Circuits 2nd Inverter Technology Scaling  Die size is used to increase by 14% per generation  Technology generation spans 2-3 years

© Digital Integrated Circuits 2nd Inverter Technology Evolution International Technology Roadmap for Semiconductors Max  P power [W] Max frequency [GHz],Local-Global Bat. power [W] Wiring levels Supply [V] Technology node [nm] Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/13nm

© Digital Integrated Circuits 2nd Inverter Technology Evolution

© Digital Integrated Circuits 2nd Inverter Technology Scaling (1) Minimum Feature Size

© Digital Integrated Circuits 2nd Inverter Technology Scaling (2) Number of components per chip

© Digital Integrated Circuits 2nd Inverter Technology Scaling (3) t p decreases by 13%/year 50% every 5 years!

© Digital Integrated Circuits 2nd Inverter Technology Scaling (4) From Kuroda

© Digital Integrated Circuits 2nd Inverter  Processor Scaling P.Gelsinger: “  Processors for the New Millenium”, ISSCC 2001

© Digital Integrated Circuits 2nd Inverter  Processor Power P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

© Digital Integrated Circuits 2nd Inverter  Processor Performance P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

© Digital Integrated Circuits 2nd Inverter Technology Scaling Models

© Digital Integrated Circuits 2nd Inverter Scaling (long Channel Devices)

© Digital Integrated Circuits 2nd Inverter Scaling (short-channel devices)

© Digital Integrated Circuits 2nd Inverter Scaling (short-channel devices)

© Digital Integrated Circuits 2nd Inverter 2016 Outlook  Performance 2X/16 months  1 TIP (terra instructions/s)?  2GHz VS 30GHz clock (building super-computers with multi-core maybe the promising solution!!!)?  Size  No of transistors: 10 Billion?  Die: 60*60 mm?  Power  Total <200mW ?  Leakage: more than 1/3 of the active Power? P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

© Digital Integrated Circuits 2nd Inverter Questions  What will cause this model to break?  Power and power density  Leakage  Process Variation  When will it break?  Will the model gradually slow down?  Dead of CMOS? New technology?