Proposed AP2 line BPM readout card 1. Variation on a theme – based on debuncher LLRF boards. Reuse uController, CPLD, Ethernet, SDRAM, Software 2. Nim.

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Presentation transcript:

Proposed AP2 line BPM readout card 1. Variation on a theme – based on debuncher LLRF boards. Reuse uController, CPLD, Ethernet, SDRAM, Software 2. Nim format, connects to ACNet via ethernet, local serial port for debug, download 4. On board synthesizer to generate 53MHz from 10MHz reference using DDS in numerically controlled divider configuration, or lock to 53MHz reference 3. Downconvert using AD8348 quadrature demodulator chip. Do low pass in analog. Digitize low pass output at 21MHz – ~35 samples per transfer 5. On board high speed DAC to generate test signals (e.g. self-test possible) 6. Large memory to hold long data records (readout optional); uController could be used for data reduction 7. LVDS port to exchange data, timing with other boards (optional) Ashmanskas, Hansen, Peterson 7/21/04

SD RAM 16Mx16 EthRd Eth Ad Eth Dat Debuncher Transfer Line BPM Card (2 BPMs/card) D A 10/53MHz Ø Det Sync I/O IN 0 A EP1C6 Cyclone FPGA 10 Bit A/D 2RF/7 Ref FB EthWrt USB MSP430 uC A D Rd Wrt Ethernet WizNet IIM7010A I/Q Dat 10 Bit A/D 53MHz VXO Err Amp Sdat I/O 53MHz I/O RJ-45 Spare I/O Lo Pass AD8348 IN 0 B 10 Bit A/D 2RF/7 I/Q Dat 10 Bit A/D Lo Pass AD8348 IN 1 A 10 Bit A/D 2RF/7 I/Q Dat 10 Bit A/D Lo Pass AD8348 IN 1 B 10 Bit A/D 2RF/7 I/Q Dat 10 Bit A/D Lo Pass AD8348 2RF Ashmanskas, Hansen, Peterson 7/21/04 AD9952 DDS AD9201 x 4 SysClk

AD 8348 Ashmanskas, Hansen, Peterson 7/21/04

Post processing of Oscilloscope trace Multiply by quadrature square wave to approximate mixer. Follow with 4 pole IIR to approximate analog low pass Multiply by Sine, Cosine follow with 100 nsec boxcar to show feasibility of oscilloscopes as BPMs Oscilloscope trace with inline bandpass filter 5mV/Div Ashmanskas, Hansen, Peterson 7/21/04

Cost and Schedule Ball park cost $500 per NIM card. Four BPM plates per card Schematic is in progress. First pass next week Board fab 10 working days Layout – 2 to 3 weeks after sign off on schematic Initial debug of prototype 2 weeks. Software – first pass 2 weeks – talks to ethernet, reports raw data after being triggered; reporting sum, difference/sum to acnet is easy; more esoteric features TBD The plan is to having something ready to go in for testing by the end of the shutdown Ashmanskas, Hansen, Peterson 7/21/04 We need to start ordering parts soon (can we do so next week?) Assembly of first prototype 2-3 days.