ClicPix ideas and a first specification draft P. Valerio

The source of the error… 2 The leakage power consumption was calculated using a power measurement on a shift register using the same technology (and dividing by the number of flip- flops in the chain) A little error in reading the plot caused a miscalculation of 3 orders of magnitude… It’s actually MILLIAMPS!

… and the updated power budget 3 Bunch ONOFFONSleep Analog C[0:N] ONIdleONSleep Digital C[0] ReadOut ONIdleONSleep Digital C[1] ReadOutIdle ON Sleep Digital C[N] ReadOutIdle 20ms Pixel AnalogON Pixel DigitalON Periphery AnalogON Periphery DigitalON IO LVDS PadsOFF Bunch Train (3.0 W/cm 2 ) Pixel AnalogOFF Pixel DigitalON Periphery AnalogOFF Periphery DigitalON IO LVDS PadsON Chip Readout (360 mW/cm 2 ) Pixel AnalogOFF Pixel DigitalIdle Periphery AnalogOFF Periphery DigitalON IO LVDS PadsOFF Idle (7.8 mW/cm 2 ) Readout Time

4 64x64 array (25 microns) 64x64 array (20 microns) Die area 3 mm 2 mm Area left for the periphery and pads Chip floorplan 1 mm clearance for sensor bonding Pads Sensor

Sensor bonding 5 The chip will be functionally complete and it will be usable as a tracking detector (although it will have a smaller size and it will lack some automatic controls for debug purposes) Testing the demonstrator in a beam or with a radioactive source would be ideal to fully test its performances and characterize it In order to acquire data from a source, a sensor needs to be bonded to the chip. There are some problems in doing it: – The foundry will not give us any full wafer as the project will be implemented in a MPW – The pitch of the bonding is very small. Advanced technologies (copper pillars, indium bumps) will be needed – The pitch can be relaxed if we decide to bond only one every four pixels

Pixel logic 6 Each pixel includes simultaneous 4-bits TOA and 4-bits TOT measurements using a reference 100 MHz clock The clock is distributed along each column exploiting the delays of buffers to give each pixel an “incoherent” clock signal, in order to simplify the clock distribution tree and to avoid a synchronous switch of every pixel in the matrix (which would affect the stability of the power supply) The readout is on a per-column basis, distributing the full 320 MHz clock (for a DDR bandwidth of 640 Mbps) A compression logic allows skipping pixels which were not hit during the acquisition. A cluster-based compression is being evaluated Power saving techniques include clock gating when the pixel is not being read out and power gating (with an external signal) for the analog part when the chip is not acquiring data

Shutter Load_conf Readout Poweroff Analog_bias To the periphery Pixel block diagram 7 4 bits TOT To the pixel above To the pixel below Clk Data ClkData Mask, TP Disc_out Data Compression logic Analog Frontend 4 bits TOA HF Enable logic 4 bits tuning DAC Clock divider

Analog pixel electronics 8 I KRUM /2 M FB1 CFCF C TEST M FB2 M LEAK C LEAK CLCL I KRUM V out V in I det V FBK V dout C BUF gmgm V th DAC V test A current DAC provides threshold tuning to calibrate the array A test capacitor is included to inject test pulses in the frontend The biasing point can be globally tuned using DACs in the periphery Bonding Pad

Power pulsing 9 The analog part of the pixel uses too much power by itself. It’s necessary to implement a controlled power down when the chip is not acquiring data A preliminary calculation sets the time the analog frontend can be on to be not more than 100 μs. In order to be functional, however, the circuits need some time to settle (around 20 μs) In order to make the requirements for the power supply more relaxed, each column can be turned on at a different time to gradually turn on each chip t Power Bunch crossing ~15 μs20 μs

Periphery and end-of-column 10 A periphery logic with a 14-bit command register will be implemented to control all the features of the chip. This logic will generate control signals for the various parts of the periphery and of the pixel array reading serial commands from an external pin DACs will be implemented to generate reference voltages. An external absolute voltage reference will be needed due to the lack of a band-gap block Configuration data (e.g. for calibration) are sent serially to each pixel, one bit per column, in order to reduce the speed of the clock in the array The periphery will also include a block that automatically select which clock signal (if any) will be sent to the pixel array, between the counting clock (used for TOT and TOA measurements) and the readout clock

Periphery block diagram 11 Data_in_column To next column Periphery State Machine Data IN 14-bits command register DACs (and their config registers) Load_conf Readout Readout MUX Data OUT Data_out_column Clock gating logic Clk_readout Clk_acquisition clk V_bias Poweroff Test_pulse Analog_bias Shutter End of column block

Available commands 12 Readout data1, 2, 4 columns or full chip Write per-pixel configuration data1, 2, 4 columns or full chip Write global configuration registersBiasing DACs, timings Reset array Shutter controlvia external pin Analog poweroffvia external pin Send analog test pulsevia external pin (after array configuration)

Future plans for the design 13 The submission is scheduled for November, so it’s important to finalize the specifications as soon as possible Analog blocks were already designed for a test chip and they require minor modifications. Digital blocks are being developed Some blocks (especially in the pixel) are very similar to the SmallPix design, resulting in code and ideas sharing that can benefit both projects This demonstrator lacks a few “standard” blocks, such as a PLL or a band- gap. They are necessary in many projects and, as more and more people start using 65 nm technology, they will become available