PACS IBDR 27/28 Feb 2002 Digital Processing Unit1/16 DPU PRESENTATION R.Orfei & S. Pezzuto CNR- IFSI.

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Presentation transcript:

PACS IBDR 27/28 Feb 2002 Digital Processing Unit1/16 DPU PRESENTATION R.Orfei & S. Pezzuto CNR- IFSI

PACS IBDR 27/28 Feb 2002 Digital Processing Unit2/16 Design status (1/2) -Design Completed for the HW boards (contracted to Carlo Gavazzi Space): - CPU Board - I/F Board - DC/DC Converter Board - Motherboard -First set of boards delivered beginning of November DC/DC Converter to be delivered on 25-2-’02

PACS IBDR 27/28 Feb 2002 Digital Processing Unit3/16 DESIGN STATUS (2/2) Cabling between Motherboard and Front Wall Connectors finished Design and manufacture of the box finished AVM SW: S/C IF (nominal mode): 100% (burst mode): under testing Controller: 100% HK monitoring: 100% Procedure handling: 100% (coding single proc.) 1355 I/F: porting drivers under VIRTUOSO

PACS IBDR 27/28 Feb 2002 Digital Processing Unit4/16 OBS ARCHITECTURE DESIGN

PACS IBDR 27/28 Feb 2002 Digital Processing Unit5/16 BUDGETS FOR FM (1/2) (ACTUAL MASS INFERRED FROM AVM BOARDS) Box weight (mechanics):3037 g CPU Boards (2 of): 960 g I/F Boards (2 of): 640 g DC/DC Boards (2 of) (E):1000 g Motherboard: 520 g Screws etc.: 100 g Cabling (E): 300 g Conformal coating (E): 420 g TOTAL (E) 6977 g (+-200 g)

PACS IBDR 27/28 Feb 2002 Digital Processing Unit6/16 BOX INTERFACE CONTROL DRAWING

PACS IBDR 27/28 Feb 2002 Digital Processing Unit7/16 BUDGETS FOR FM (2/2) TOTAL ESTIMATED POWER (DC/DC CONVERTER EFFICIENCY = 70%): 14.6 W

PACS IBDR 27/28 Feb 2002 Digital Processing Unit8/16 CPU BOARD DSP RAM FPGA EPROM 20 MHz 1355 MEZZANINE JTAG

PACS IBDR 27/28 Feb 2002 Digital Processing Unit9/16 I/F BOARD FIFOS S/S I/FsA/D Conv. 16 MHz 1553B ( S/C I/F) Long Stub Trafos “A” and “B” FPGA

PACS IBDR 27/28 Feb 2002 Digital Processing Unit10/16 CPU+I/F+Motherboard assembled during preliminary tests at CGS JTAG In Circuit Emulator (ICE) ICE Computer Monitor Power Supplies Motherboard

PACS IBDR 27/28 Feb 2002 Digital Processing Unit11/16 AIV FLOW

PACS IBDR 27/28 Feb 2002 Digital Processing Unit12/16 SCHEDULES (1/4)

PACS IBDR 27/28 Feb 2002 Digital Processing Unit13/16 SCHEDULES (2/4)

PACS IBDR 27/28 Feb 2002 Digital Processing Unit14/16 SCHEDULES (3/4)

PACS IBDR 27/28 Feb 2002 Digital Processing Unit15/16 SCHEDULES (4/4)

PACS IBDR 27/28 Feb 2002 Digital Processing Unit16/16 PA/QA ACTIVITIES ALL COMPONENTS ARE BOUGHT THROUGH THE CO-ORDINATED PARTS PROCUREMENT AGENCY FOR INDUCTORS AND TRANSFORMERS RELEVANT RFAs AND PADs ARE ISSUED NO RE-FLOW SOLDERING IS FORESEEN: ALL HAND MADE SOLDERS BY ESA QUALIFIED PERSONNEL ENVIRONMENTAL QUALIFICATION TESTS ARE SCHEDULED FOR QM UNITS ENVIRONMENTAL ACCEPTANCE TESTS ARE SCHEDULED FOR FM UNITS