Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Operating Systems Lecture 4 Computer Systems Review Read: Chapter 2

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Computer System Components Computer system components: CPU I/O controllers (e.g. disk controller) Memory Controller The CPU and device controllers can operate concurrently. The Memory controller ensures orderly access to shared memory.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Computer-System Architecture

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Interrupt Driven O.S. Most modern operating systems are interrupt driven. Start-up: 1) Load O.S. (kernel) and start it running. 2) O.S. waits for an event (an interrupt). Definition of interrupt: An interrupt is a method to ensure that the CPU takes note of an event. Types of interrupt: Hardware interrupts (e.g. from an I/O device) Software interrupt (from an executing process. System Call) Also called a trap or an exception Generated to signal error (e.g. divide by zero) or to request service from OS (e.g. I/O).

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Interrupt Handling The operating system preserves the state of the CPU by storing registers and the program counter. The O.S. determines which type of interrupt has occurred by one of two methods:  polling each device ("Did you interrupt me?")  vectored interrupt system (Table of addresses) Separate segments of code determine what action should be taken for each type of interrupt. The OS executes the sequence of commands associated with the given interrupt. The OS recovers the stored information from the original process and continues execution.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Interrupt Time Line For a Single Process Doing Output

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Synchronous I/O Synchronous I/O: After I/O starts, control returns to user program only upon I/O completion.  Process requests I/O  CPU sends I/O request to device controller  CPU waits for I/O to finish (signalled by interrupt)  Continue executing original process (after handling interrupt)  At most one I/O request is outstanding at a time, no simultaneous I/O processing. Problem: I/O is slow. CPU is idle while waiting for I/O to finish.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Asynchronous I/O After I/O starts, control returns to user program without waiting for I/O completion.  Process requests I/O  CPU sends request to device controller  CPU continues to process instructions (either previous process or another one).  Interrupt signals I/O completion  CPU processes interrupt Less time is used to process I/O requests using asynchronous I/O than with synchronous I/O.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Two I/O Methods Synchronous Asynchronous

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Other Considerations When using asynchronous I/O, there may be multiple I/O requests at the same time. Requests for multiple devices Multiple requests for a single device. A device-status table keeps track of the requests. It stores: Device type Device address Device State (not-functioning, idle, busy) Wait queues list multiple requests for a single device.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Device-Status Table

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Direct Memory Access Structure If only 1 character is transferred per I/O request, then an interrupt is generated after each character is transferred. Slow I/O device (e.g. modem): ~1 ms/char = 1000  s/char Time needed to process interrupt: ~2  s This leaves 998  s for processing other things. Fast I/O device (e.g. hard disk): ~4  s/char Only leaves 2  s to process other things. Solution: Direct Memory Access (DMA) Used for high speed I/O devices. Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention Only one interrupt is generated per block, rather than the one interrupt per byte.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Storage Structure The Fetch-Execute Cycle: Computer programs must be in main memory to be executed. The CPU fetches the next instruction (from the address stored in the instruction counter) The CPU executes the instruction: This may involve fetching operands from main memory. It may also involve storing the result in main memory. Ideally, we would want all programs stored in main memory. This is impractical because: Main memory is too small to store all needed programs and data. Main memory is volatile. It loses its contents when the power goes off.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Secondary Storage Main memory – only large storage media that the CPU can access directly. Secondary storage – extension of main memory that provides large nonvolatile storage capacity. Most common type of secondary storage:  Magnetic disks – rigid metal or glass platters covered with magnetic recording material  Disk surface is logically divided into tracks, which are subdivided into sectors.  The disk controller determines the logical interaction between the device and the computer. Other types of storage: Cache, CD_ROM, Magnetic tape.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Moving-Head Disk Mechanism

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Storage Hierarchy Storage systems organized in hierarchy.  Speed  Cost  Volatility The fastest memory is the most expensive and most volatile. Used for CPU registers. As move down the hierarchy, memory gets slower and cheaper. Non-volatile memory is the slowest.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Storage-Device Hierarchy

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Caching Accessing main memory can be slow compared to the time it takes to execute instructions. Caching is the use of high-speed memory to hold recently- accessed data. Blocks of instructions or data from main memory are transferred to a smaller, faster memory: the cache. Locality of reference ensures efficient use of the cache:  As a process executes, it references memory in clustered areas.  Nearby memory locations are likely to be accessed in the near future.  Therefore, when one item is requested from main memory, an entire block is transferred to the cache. Use of a cache requires a cache management policy. Caching introduces another level in storage hierarchy. This requires data that is simultaneously stored in more than one level to be consistent.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Maintaining Consistency An operating system needs to maintain consistency at different levels of the storage system. Example: Suppose an integer, A, is stored in a file, B, on the disk. Suppose we want to increment A by 1. A is copied from disk to main memory. A is copied from main memory to cache A is copied from the cache to a register. We now have 4 copies of A. A is incremented in the register. Now A has different values in different locations. The OS must ensure that any process wanting to access A gets the most recently updated version.

Silberschatz, Galvin and Gagne  2002 Modified for CSCI 399, Royden, Operating System Concepts Migration of A From Disk to Register