Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Phase 5 Pad Placement / Optimisations Martin Kittel

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Chip with Pads Slide 2 Pad Ring Inner Core Interconnect

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Ordered Pads Slide 3 O3O3 O2O2 O1O1 I0I0 PO0O0 I1I1 I3I3 I2I2 I4I4 O4O4 G

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Improve Pad placement Long Interconnects high R slow chip Reduce length of interconnects Place Pads after placing standard cells Place standard cells with Pads in mind Slide 4

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Place Pads to minimize overall wire length Slide 5 O1O1 O2O2 O0O0 I2I2 PI1I1 I0I0 O3O3 I3I3 I4I4 O4O4 G

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock No consideration of critical I/O Slide 6 O1O1 O2O2 O0O0 I2I2 PI1I1 I0I0 O3O3 I3I3 I4I4 O4O4 G Critical Inputs: I 0, I 3 Critical Outputs: O 3, O 4

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Place critical I/O near to a Pad Slide 7 O3O3 O1O1 O0O0 I2I2 PI1I1 I0I0 O2O2 I3I3 I4I4 O4O4 G Critical Inputs: I 0, I 3 Critical Outputs: O 3, O 4

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Thank you for your attention!