(-133)*33+44*14.5

133*33+44*14 Input device memory calculator Output device controller Control bus data bus memory

Chapter 3

(-133)*33+44*14.5 Where do we store our data and code? How can we get them?

Store program and data in memory Find them by their addresses Addressing mode is based on the architecture of CPU.

Chapter 3: Microprocessor and its Architecture 3.1 Internal Microprocessor Architecture 3.2 Real Mode Memory Addressing 3.3 Protected Mode Memory Addressing

3.1 Internal Microprocessor Architecture

8+6 MOV AL,8 MOV BL,6 ADD AL,BL

3.1 Internal Microprocessor Architecture

The programming model of the Intel 8086 through the Petium II is in Figures following. The shaded areas registers exits only on the through the Petium II.

3.1 Internal Microprocessor Architecture AH AL BH BL CH CL DH DL SP BP DI SI AX BX CX DX SP BP DI SI Accumulator Base index Count Data Stack pointer Base pointer Destination index Source index Multipurpose Registers DR PR IR 16 bits

3.1 Internal Microprocessor Architecture IP FLAGS IP FLAGS Instruction pointer Flags CS DS ES SS Code 16bit Data Extra Stack Special purpose registers Segment registers

3.1 Internal Microprocessor Architecture AH AL BH BL CH CL DH DL SP BP DI SI EAX EBX ECX EDX ESP EBP EDI ESI Accumulator Base index Count Data Stack pointer Base pointer Destination index Source index Multipurpose Registers DR PR IR 32 bit

3.1 Internal Microprocessor Architecture IP FLAGS EIP EFLAGS Instruction pointer Flags CS DS ES SS FS GS Code Data Extra Stack Special purpose registers Segment registers

3.1 Internal Microprocessor Architecture Registers Operations EAXADD,SUB,I/O EBXTRANSFER ECXCYCLE EDXMUL,DIV,I/O EIPInstructor pointer EBPBase pointer ESPStack pointer

3.1 Internal Microprocessor Architecture EFLAGSC,P,A,Z,I,O…… CScode segment DS data segment ESAdditional data Segment SSstack segment

3.1 Internal Microprocessor Architecture OFOF DFDF IFIF TFTF SFSF ZFZF UAFAF UPFPF UCFCF FLAG of 8086 Undefined CarryParity Auxiliary carry zero sign trap interrupt direc tion overflow

3.2 Real Mode Memory Addressing

We can get those data by their addresses. But how? Real mode memory addressing can do that. It can be used in 8086 and above.

3.2 Real Mode Memory Addressing Real mode memory addressing Physical address = (segment address)*10H + offset address Offset address Ranges from 0000H to FFFFH 8 bit 00000H 0FFFFFH 10001H 10002H

CS =0000H Offset 0000H, 0FFFFH CS + offset = 00000H,-----0FFFFH CS = 0001H Offset 0000H, 0FFFFH CS + offset = 00010H, FH More examples on table 2.1

3.2 Real Mode Memory Addressing 8 bit 00000H 0FFFFFH 10001H 10002H 8 bit DATA SEGMENT CODE SEGMENT DS = 1000H CS

3.2 Real Mode Memory Addressing 1FFFF 1F Segment register k a memory segment offset F Physical address 1F000 FFFFF Max Physical Address is 1M

3.2 Real Mode Memory Addressing In real mode the length of memory segment is 64k(FFFFH). segment end address = segment start address + FFFFH

3.2 Real Mode Memory Addressing The rules of memory addressing define a default combination of segment register and offset register.( 存储段地址 和偏移量地址的寄存器有规定的组合方 式 ).

3.2 Real Mode Memory Addressing Combination is: –CS+IP/EIP locating the next instruction in code segment –SS+SP/ESP or SS+BP/EBP locating data in stack segment –DS+ memory offset locating data in data segment The max offset is 64k

3.2 Real Mode Memory Addressing Combination is: –When EIP/ESP/EBP is used in an instruction, only the left 16 bits are available as the offset address whose value is from 0 to 0FFFFH. –See paragraph 2. The max offset is 64k

3.2 Real Mode Memory Addressing Segment and offset addressing scheme allows relocation. Move the program to a new area of memory without changing the offset, but only change the contents of the segment registers. Segment start address is allocated by DOS.

3.2 Real Mode Memory Addressing Now we have learned about multipurpose registers, special-purpose registers and real mode memory addressing.

00000H 0FFFFFH 1FFFFH 2FFFFH 49000H 58FFFH MEMMORY 1M ES 20000H DS 0FFFFH Figure 2.4 REAL MODE MEMORY ADDRESS CS SS 34000H 34FFFH 64K

Figure 2.5 STACKSTACK DATADATA CODECODE 00000H 0FFFFFH 0A0EFH 0A27FH 0A0F0H CS 090F0H DS 0A280H 0A47FH SS 64K

3.2 Real Mode Memory Addressing The max physical address is FFFFFH in real mode memory addressing. So we can only find 1M memory. Question : If we have a memory of 128M, how can we get their address in the mode? Are the left 127M disabled?

3.3 Protected Mode Memory Addressing

Protected mode memory addressing is used in and above. For and above the max physical address is 4G in this mode.

3.3 Protected Mode Memory Addressing

PROTECT MODE MEMORY ADDRESSING –Physical address = base address + offset selector Segment register descriptor Local/Global descriptor table1(8192*2) Right Base address (24/32 bits) Limit Segment base address Segment length From operand

3.3 Protected Mode Memory Addressing

See p59 2.6