University of Tehran 1 Microprocessor System Design Processor Timing

University of Tehran 2 Outline Machine cycle Fetch, decode, execute Processor timing Bus cycles Memory / IO read Memory / IO write

University of Tehran 3 Where is a program stored? ;assume that initially ;ds = 2000, bx = 0023, ax = 351C ;cs = 1000, ip = 0005 mov[bx], al;8807 hlt;F4

University of Tehran 4 How does the  P works? Fetch Increment Program Counter (CS:IP) by 1 Decode Execute

University of Tehran 5 CS:IP FETCH

University of Tehran :0005 FETCH

University of Tehran FETCH

University of Tehran LOW HIGH FETCH

University of Tehran LOW HIGH FETCH

University of Tehran LOW HIGH FETCH

University of Tehran 11 INC. PC

University of Tehran 12 INC. PC

University of Tehran 13 DECODE mov [bx], ?

University of Tehran 14 CS:IP FETCH

University of Tehran :0006 FETCH

University of Tehran FETCH

University of Tehran LOW HIGH FETCH

University of Tehran LOW HIGH FETCH

University of Tehran LOW HIGH FETCH

University of Tehran 20 INC. PC

University of Tehran 21 INC. PC

University of Tehran 22 DECODE mov [bx], al

University of Tehran 23 DS:BX EXECUTE mov [bx], al

University of Tehran :0023 EXECUTE mov [bx], al

University of Tehran EXECUTE mov [bx], al

University of Tehran C EXECUTE mov [bx], al

University of Tehran C HIGH LOW EXECUTE mov [bx], al

University of Tehran C HIGH LOW EXECUTE mov [bx], al

University of Tehran 29 CS:IP FETCH

University of Tehran :0007 FETCH

University of Tehran FETCH

University of Tehran LOW HIGH FETCH

University of Tehran F4 LOW HIGH FETCH

University of Tehran F4 LOW HIGH FETCH

University of Tehran F4 LOW HIGH INC. PC

University of Tehran F4 LOW HIGH INC. PC

University of Tehran F4 LOW HIGH DECODE hlt

University of Tehran 38 EXECUTE hlt

University of Tehran 39 Machine Cycle

University of Tehran 40 Machine Cycle Timing Diagram

University of Tehran 41

University of Tehran 42 Processor Timing

University of Tehran 43 Processor Timing Diagram for the 1st fetch machine cycle (M1) of instruction mov [bx],al

University of Tehran 44 Processor Timing Diagram for the 2nd fetch machine cycle (M2) of instruction mov [bx],al

University of Tehran 45 Processor Timing Diagram for the execute machine cycle (M3) of instruction mov [bx], al

University of Tehran 46 Processor Timing Diagram for the 1st fetch machine cycle (M1) of instruction hlt

University of Tehran 47 Processor Timing Diagram for any memory read machine cycle

University of Tehran 48 Processor Timing Diagram for any memory write machine cycle

University of Tehran 49 Processor Timing Diagram for any I/O read machine cycle

University of Tehran 50 Processor Timing Diagram for any I/O write machine cycle