Presenting: Yaron Yagoda Kobi Cohen DSP SWITCH Digital Systems Laboratory Winter 2002-2003 Supervisor: Isaschar Walter Semester A final Presentation.

Slides:



Advertisements
Similar presentations
Nios Multi Processor Ethernet Embedded Platform Final Presentation
Advertisements

Bus Specification Embedded Systems Design and Implementation Witawas Srisa-an.
Engineer Training XL1200 Electronics. Engineer Training XL1200 Electronics Confidential 2 XL1200 Electronics The XL Jet Electronic System consists of.
Internal Logic Analyzer Final presentation-part B
Internal Logic Analyzer Final presentation-part A
Performed by: Gadit Ben-Habib Dan Porat Instructor: Inna Rivkin המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory.
Mid semester Presentation Data Packages Generator & Flow Management Data Packages Generator & Flow Management Data Packages Generator & Flow Management.
Students: Nir Engelberg Ezequiel Hadid Supervisor: Mony Orbach In association with: November 23, Winter 2004.
Students: Nir Engelberg Ezequiel Hadid Supervisor: Mony Orbach In association with: September 28, Winter 2005.
High speed digital systems laboratory Part A - Presentation Project Name: Serial Communication Analyzer Presenter Name: Igal Kogan Alexander Rekhelis.
Characterization Presentation Spring 2006 Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System.
1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 12/5/2003 Multi-channel Data Acquisition System Mid-Term Presentation.
Performed by : Rivka Cohen and Sharon Solomon Instructor : Walter Isaschar המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון.
DSP Algorithm on System on Chip Performed by : Einat Tevel Supervisor : Isaschar Walter Accompanying engineers : Emilia Burlak, Golan Inbar Technion -
Presenting: Yaron Yagoda Kobi Cohen VERSITILE COMMUNICAION BETWEEN MULTI DSPS Digital Systems Laboratory Spring 2003 Supervisor: Isaschar Walter Final.
Workload distribution in satellites Part A Final Presentation Performed by :Grossman Vadim Maslovksy Eugene Instructor:Rivkin Inna Spring 2004.
Project name: Interface of DSP to Peripherals of PC Supervisor: Broodney, Hen | Presenting: Yair Tshop Michael Behar בס " ד.
1 Network Packet Generator Characterization presentation Supervisor: Mony Orbach Presenting: Eugeney Ryzhyk, Igor Brevdo.
Fast Ethernet Card With Utopia Interface Performed by:Anat Gavish Tomer Schatzberger Tomer Schatzberger Instructor: Boaz Mizrachi הטכניון - מכון טכנולוגי.
Students: Asulin Ofir Heller Itai Supervisor: Mony Orbach In association with: June 16, summer 2006.
1 Project supervised by: Dr Michael Gandelsman Project performed by: Roman Paleria, Avi Yona 26/4/2004 Multi-channel Data Acquisition System Final_A Presentation.
Presenting: Yaron Yagoda Kobi Cohen DSP SWITCH Digital Systems Laboratory Winter Supervisor: Isaschar Walter Mid-Term Presentation.
Reliable Data Storage using Reed Solomon Code Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl Spring 2004 Midterm Presentation.
1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab.
Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי.
1 FINAL PRESENTATION PART A Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System architectures.
Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי.
Interface of DSP to Peripherals of PC Spring 2002 Supervisor: Broodney, Hen | Presenting: Yair Tshop Michael Behar בס " ד.
Students: Nir Engelberg Ezequiel Hadid Supervisor: Mony Orbach In association with: January 3, Winter 2005.
PowerBench Programmable Power Supply Dror Lazar Moran Fishman Supervisor: Boaz Mizrahi Winter Semester 2009/10 HS DSL.
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
1 Mid-term Presentation Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System architectures.
Final Presentation Momentum Measurement Card Project supervised by: Mony Orbach Project performed by: Hadas Preminger, Uri Niv.
Presenting: Yaron Yagoda Kobi Cohen DSP SWITCH Digital Systems Laboratory WINTER-SPRING ‏2003 Supervisor: Isaschar Walter Characterization Presentation.
CERN CMS Project Host / SD Card Configuration Data Access Dave Ojika Alex Madorsky Dr. Darin Acosta Dr. Ivan Furic.
System Architecture A Reconfigurable and Programmable Gigabit Network Interface Card Jeff Shafer, Hyong-Youb Kim, Paul Willmann, Dr. Scott Rixner Rice.
Midterm Presentation Project Name: Serial Communication Analyzer Company Name: Digital laboratory Presenter Name: Igal Kogan Alexander Rekhelis Instructor:
PCI-Express Network Sniffer Characterization Presentation Project Period : 2 semesters Students: Neria Wodage Aviel Tubul Advisor: Mony Orbach 17/12/2007.
Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters
Wireless PC-Peripherals Communication via Blue Tooth (D0130 project)
The 6713 DSP Starter Kit (DSK) is a low-cost platform which lets customers evaluate and develop applications for the Texas Instruments C67X DSP family.
EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)
High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/ Semester Project Date:
Final Year Project Presentation A Remote FPGA Laboratory Environment David Hehir 4 th Year EE Supervisor: Fearghal Morgan.
Sub- Nyquist Sampling System Hardware Implementation System Architecture Group – Shai & Yaron Data Transfer, System Integration and Debug Environment Part.
Ross Brennan On the Introduction of Reconfigurable Hardware into Computer Architecture Education Ross Brennan
“ Analyzer for 40Gbit Ethernet “ (Bi-semestrial project) Executers: פריד מחאג ' נה Farid Mahajna Husam Kadan חוסאם קעדאן Instructor:
By: Oleg Schtofenmaher Maxim Fudim Supervisor: Walter Isaschar Characterization presentation for project Winter 2007 ( Part A)
OPTO Link using Altera Stratix GX transceiver Jerzy Zieliński PERG group Warsaw.
GBT Interface Card for a Linux Computer Carson Teale 1.
High Speed Digital Systems Lab Asic Test Platform Supervisor: Michael Yampolsky Assaf Mantzur Gal Rotbard Project Midterm Presentation One-Semester Project.
1 Abstract & Main Goal המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory The focus of this project was the creation of an analyzing device.
Performed by: Yaron Recher & Shai Maylat Supervisor: Mr. Rolf Hilgendorf המעבדה למערכות ספרתיות מהירות הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל.
Part A Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.
PROJECT - ZYNQ Yakir Peretz Idan Homri Semester - winter 2014 Duration - one semester.
Reconfigurable Communication Link Between FASTER and RTSim Interface Matthew McCollum Mark Krause Derek Keibler.
Final Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.
Project D1427: Stand Alone FPGA Programmer Final presentation 6/5/10 Supervisor: Mony Orbach Students: Shimrit Bar Oz Avi Zukerman High Speed Digital Systems.
Presented by: Reshef Schreiber Itay Leibovitz Instructed by: Eran Segev.
Technion - Israel institute of technology department of Electrical Engineering High speed digital systems laboratory 40Gbit Signal Generator for Ethernet.
Serial Communication Analyzer Company Name: Digital laboratory Presenter Name: Igal Kogan Alexander Rekhelis Instructor: Hen Broodney Semester:Winter/Spring.
Part A Final Dor Obstbaum Kami Elbaz Advisor: Moshe Porian August 2012 FPGA S ETTING U SING F LASH.
1 Performed by: Kobi Cohen,Yaron Yagoda Instructor: Zigi Walter המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי.
Performed by: Yarovoy Boris Dubossarsky Maxim Instructor: Michael Itzkovitz המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון.
High Speed Digital Systems Lab Spring/Winter 2010 Project definition Instructor: Rolf Hilgendorf Students: Elad Mor, Ilya Zavolsky Integration of an A/D.
Sub- Nyquist Sampling System Hardware Implementation System Architecture Group – Shai & Yaron Data Transfer, System Integration and Debug Environment Part.
Internal Logic Analyzer Characterization presentation By: Moran Katz and Zvika Pery Mentor: Moshe Porian Dual-semester project Spring 2012.
Hardware/Software Co-Verification with RTOS Application Code Michael Bradley, Mentor Graphics Kainian Xie, Hyperchip Inc.
Internal Logic Analyzer Middle presentation-part A By: Moran Katz and Zvika Pery Mentor: Moshe Porian Dual-semester project Spring 2012.
Altera Stratix II FPGA Architecture
Presentation transcript:

Presenting: Yaron Yagoda Kobi Cohen DSP SWITCH Digital Systems Laboratory Winter Supervisor: Isaschar Walter Semester A final Presentation

PROJECT GOALS A.Adjusting hardware architecture according to specific signal processing software dataflow. B.Designing and implementing a flexible topology of communication(using the McBSP Protocol) between several DSPs and the PC.

Problem Description DSP Hardware complexity of O(N^2)

GENERAL DESCRIPTION DSP PCI CORE PCI BUS DSP -GUI -DRIVER ALTERA FLEX 10KE Switch Matrix

BLOCK DIAGRAM DSP ALTERA FPGA PCI CORE McBSP PROTOCOL PCI BUS DSP

BLOCK DIAGRAM )for pipelined connection) DSP ALTERA FPGA PCI CORE McBSP PROTOCOL PCI BUS DSP

ALTERA DEVELOPMENT CARD

McBSP PIN DESCRIPTION PinI/O Description CLKROReceive clock CLKXOTransmit clock DR IReceived serial data DX OTransmitted serial data FSR IReceive frame synchronization FSXOTransmit frame synchronization

McBSP SIGNALS

FPGA STRUCTURE Pci core Local Side application

The Local Side Application The Switch Matrix Main Control Dx Fx Dr clkr clkx Fr DSPs FROM PCI CORE

CONTROL STRUCTURE TO PCI CORE Main Control Read Enable signals Read Structures Configuration Write Structures Configuration PC read PC write

Main Control The Main control unit has the following three main tasks: 1. Configuration of the connections between the DSPs. 2. Writing data to a chosen McBSP port. 3. Reading data from a chosen McBSP port.

THE SWITCH MATRIX The configuration determines for each DSP where to write its data, whether it is another DSP or the pc. The switch matrix is constantly trying to read from each one of the McBSP ports. When it is able to read certain data it transfers it to another McBSP port according to the data in it’s configuration register.

The Switch Matrix structure Reading from The McBSP Writing to The McBSP PC readPC_write Detailed on the Next slides

The Switch Matrix cont(1)

The Switch Matrix cont(2)

The Switch Matrix cont(3) PC_read From main control From McBSP Read structures To main control

The Switch Matrix cont(4) PC_write From McBSP write structures To McBSP write structures From main control

McBSP READ UNIT

McBSP WRITE UNIT

The GUI

THE GUI The GUI gives the user an easy way to configure the Switch Matrix. Through the GUI the user can define the connections between the pc and the DSPs. The GUI also allows passing data to each one of the DSPs through the driver. In the GUI we have 8 McBSP ports for the four DSPs we have,two for each one. And one port for the PC. The GUI gives us the option to write or read data to the configured DSP.

PROJECT STATUS Introduction with the pci core. Implementation of a simple Input/Output program on the Altera card. Studying and implementing the McBSP protocol. Full implementation of the switch matrix. Communication with one McBSP. Simulation of the whole system.

FURTHER GOALS Finishing the GUI. Debugging.

FURTHER DEVELOPMENTS FOR NEXT SEMESTER Implementing dynamic configuration. Writing a program in the DSP CCS that tests the project. Creating connection in hardware to all DSPs.