Limited wires. We have only one data line. Use for for bi-directional communication. Need to send: requests for data rumble pack on/off Need to receive.

Slides:

Advertisements

Similar presentations

Advertisements

Digital Logic issues in Embedded Systems. Things upcoming Remember that the first two topic talks are on 10/24 (ultrasonic distance and stepper motors)

1 Lecture 16 Timing  Terminology  Timing issues  Asynchronous inputs.

Registers and Counters

“Asynchronous” Asynchronous vs. Synchronous. “Asynchronous”“Synchronous” Asynchronous vs. Synchronous.

ELEC 256 / Saif Zahir UBC / 2000 Timing Methodology Overview Set of rules for interconnecting components and clocks When followed, guarantee proper operation.

Parul Polytechnic Institute Subject Code : Name Of Subject : Microprocessor and assembly language programming Name of Unit : Introduction to Microprossor.

Sequential Logic 1 clock data in may changestable data out (Q) stable Registers  Sample data using clock  Hold data between clock cycles  Computation.

1 Digital Design: State Machines Timing Behavior Credits : Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals.

Assume array size is 256 (mult: 4ns, add: 2ns)

EE 316 Computer Engineering Junior Lab PS/2 Keyboard.

Chapter 11 UNIX Printing. have to be root to setup a printer local printer is directly connected remote printer is a network printer print queue is nothing.

CSE 140L Lecture 4 Flip-Flops, Shifters and Counters Professor CK Cheng CSE Dept. UC San Diego.

11/19/2004EE 42 fall 2004 lecture 341 Lecture #34: data transfer Last lecture: –Example circuits –shift registers –Adders –Counters This lecture –Communications.

Asynchronous FSMs and Verilog. PLD registered output.

Serial Peripheral Interface (SPI)

CSE 140L Lecture 6 Interface and State Assignment Professor CK Cheng CSE Dept. UC San Diego 1.

Memory. The logic and arithmetic circuits we’ve seen so far have no memory. They just transform input to output. Can we make circuits that remember? Memory.

M.S.P.V.L. Polytechnic College, Pavoorchatram

ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)

Input/Output and Communication

CS 140L Lecture 4 Professor CK Cheng 10/22/02. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

111/9/2005EE 108A Lecture 13 (c) 2005 W. J. Dally EE108A Lecture 13: Metastability and Synchronization Failure (or When Good Flip-Flops go Bad)

A.Abhari CPS2131 Registers A register is a group of n flip-flops each of them capable of storing one bit of information There are two types of registers:

Sequential logic and systems

EE345: Introduction to Microcontrollers Register and Counters Prof. Ahmad Abu-El-Haija.

1 CSE370, Lecture 16 Lecture 19 u Logistics n HW5 is due today (full credit today, 20% off Monday 10:29am, Solutions up Monday 10:30am) n HW6 is due Wednesday.

Lecture 111 Lecture 11: Lab 3 Overview, the ADV7183B Video Decoder and the I 2 C Bus ECE 412: Microcomputer Laboratory.

1 ECE243 I/O Hardware. 2 ECE243 Basic Components.

Serial Port I/O Serial port sends and receives data one bit at a time. Serial communication devices are divided into: Data Communications Equipment (DCE),

SAP1 (Simple-As-Possible) Computer

Elevator Controller We’re hired to design a digital elevator controller for a four-floor building st try: Design a counter that counts up.

Fault Tolerance via the State Machine Replication Approach Favian Contreras.

DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK

Fall 2004EE 3563 Digital Systems Design EE3563 Chapter 8 Reading Assignments  8.1, ,   8.5.1, 8.5.2,  8.8  We will.

64 CONTROLLER 64 CONTROLLER AARON RIDENOUR, RYAN WOOSTER, ALEX JAECKEL.

SEQUENTIAL CIRCUITS Component Design and Use. Register with Parallel Load  Register: Group of Flip-Flops  Ex: D Flip-Flops  Holds a Word of Data 

 8251A is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication.  Programmable peripheral designed for synchronous.

© BYU 18 ASYNCH Page 1 ECEn 224 Handling Asynchronous Inputs.

Registers and Counters by Dr. Amin Danial Asham. References  Digital Design 5 th Edition, Morris Mano.

1 CSE370, Lecture 17 Lecture 17 u Logistics n Lab 7 this week n HW6 is due Friday n Office Hours íMine: Friday 10:00-11:00 as usual íSara: Thursday 2:30-3:20.

Topic: Sequential Circuit Course: Logic Design Slide no. 1 Chapter #6: Sequential Logic Design.

CHAPTER 8 - COUNTER -.

CSC 335 Data Communications and Networking

ANALYSIS OF SEQUENTIAL CIRCUITS by Dr. Amin Danial Asham.

©2008 R. Gupta, UCSD COSMOS Summer 2008 Peripheral Interfaces Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.

MicroComputer Engineering DigitalCircuits slide 1 Combinational circuits Changes at inputs propagate at logic speed to outputs Not clocked No internal.

AS Computing Data transmission. Basic data transmission Baud The rate that the voltage changes is called the Baud. If the voltage changes 10 times every.

OCRP RF Control WINLAB – Rutgers University Date : June Authors : Prasanthi Maddala, Khanh Le,

Chapter 7 Channel organization. Group members  Bilal Ahmed  Mehmal javed  Faisal khan janjua  Harris bashir.

CEC 220 Digital Circuit Design Mealy and Moore State Machines Friday, March 27 CEC 220 Digital Circuit Design Slide 1 of 16.

Embedded Communication Protocols Don Heer 10/18/10 1.

PlayStation 2 DualShock 2 Controller Ryan O’Keefe, Kabir Singh and Adrian Padin 1.

Networked Embedded Systems Pengyu Zhang EE107 Spring 2016 Lecture 8 Serial Buses.

1 Registers A register is a group of n flip-flops each of them capable of storing one bit of information There are two types of registers: parallel and.

VHDL Workshop FSM. FSM-Smart Counter Requirements Receives a start signal. When start signal goes high, starts to count from zero: reset value – 0, first.

Input/Output and Communication

Sequential logic examples

Communication Lines Fundamentals.

BJ Furman ME 106 Fundamentals of Mechatronics 15NOV2012

Presentation Test. Second Slide Third Slide It worked.

Clock Domain Crossing Keon Amini.

Counters and Registers

Serial EEPROM (Atmel 24C-512)

EECS 373 On Operational Amplifiers and Other Means of Manipulating Voltage and Current.

CHAPTER 4 COUNTER.

Lecture 19 Logistics Last lecture Today

Registers and Counters

William Stallings Computer Organization and Architecture

Presentation transcript:

Limited wires. We have only one data line. Use for for bi-directional communication. Need to send: requests for data rumble pack on/off Need to receive controller status Some slides from Aaron Ridenour, Ryan Wooster and Alex Jaeckel. http://www.eecs.umich.edu/courses/eecs373/Lec/F13Student/N64.pptx See http://www.eecs.umich.edu/courses/eecs373/Lec/StudentW14/N64%20Controller.pdf for other details.

Bi-directional Open Collector Pull-up resistor keeps the line high while idle. To send 0, the output line is pulled low and connected to ground. To send 1, nothing should be sent. Never drive the line high. Both sides do this, so bidirectional. If no data to send, wire stays (floats) high.

Controller Encoding Each bit is sent in ~4 𝜇𝑠 Logical 0: Low for 3 𝜇𝑠, followed by high for 1 𝜇𝑠 Logical 1: Low for 1 𝜇𝑠, followed by high for 3 𝜇𝑠

Controller Encoding http://inst.eecs.berkeley.edu/~cs150/sp01/Labs/lablecckpt1.ppt

Joystick x-coordinate Joystick y-coordinate start bit A B Z St reset L R |----Command (console) 0x01-----| |----Data1 (controller) 0x00------| |-------Data2 (controller) 0x00----| stop bit Joystick x-coordinate Joystick y-coordinate |--------Data3 (controller) 0x00----------| |---------Data4 (controller) 0x01-----------| Images taken from: http://afermiano.com/index.php/n64-controller-protocol

Clock Synchronization Once a FF goes metastable (due to a setup time violation, say) we can’t say when it will assume a valid logic level or what level it might eventually assume. The only thing we know is that the probability of a FF coming out of a metastable state increases exponentially with time. This and next slide from http://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf. If you have an interest in this topic, that’s a nice slide set. https://web.archive.org/web/20070203054100/http://www.caip.rutgers.edu/~bushnell/dsdwebsite/dsdlecture18.ppt has yet more details.

Traditional synchronizer SIG is asynchronous, and META might go metastable from time to time However, as long as META resolves before the next clock period SIG1 should have valid logic levels Place FFs close together to allow maximum time for META to resolve. Under reasonable assumptions, MTBF=9x1010 years. More than the age of the Earth. Could add a third.