CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Bipolar transistors.

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Presentation transcript:

CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Bipolar transistors

PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier This leads to 1-directional current flow Forms junction capacitor –Capacitance highly voltage dependent –Can be nuisance or benefits

PN Junctions

Initial impurity concentration

PN Junctions

Depletion region widths: Barrier potential:

Example NA=10^15 atoms/cm^3, ND=10^16, vD=-10 Ni=2.25*10^20 Phi_o=26ln(10^15*10^16/2.25/10^20)=638 mV xp=  m xn= 0.35  m Max field = q*NA*xp/  = -5.4*10^4 V/cm Note the large magnitude of the field

PN Junctions The depletion charge The junction capacitance

Realistic curve

Can be used as voltage controlled capacitor Here m = 1/2 for the step change in impurity concentration. For gradual concentration change, m = 1/3.

Impurity concentration profile for diffused pn junction

Current density at boundary due to wholes: Total : Diode current:

The MOS Transistor

TWO TYPES OF TRANSISTORS

Capacitors Two conductor plates separated by insulator for a capacitor Intentional capacitors vs parasitic capacitors Linear vs nonlinear capacitors Linear capacitors:

Integrated Capacitors in CMOS High density, good matching, but nonlinear

High density, good matching, good linearity, but require two-poly processes

Other Caps C gs of enhancement transistors metal to poly metal to metal PN junction –diffusion to substrate –side wall Fringe caps from top layer metals

Layering strategies

Parasitic Capacitors

Proper layout of capacitors For achieving C A = 2C B, which one is better?

Various Capacitor Errors

Resistors in CMOS Diffusion resistor polysilicon resistor well resistor metal layer resistor contact resistor

Diffusion resistor in n-well Is this resistor linear? Why?

Polysilicon resistor on FOX

n-well resistor on p-substrate

Bipolar in CMOS PNP

N+ P+ P contacts N-well P substrate PNP bipolar transistor in an N-well process Issues?

BJT in bipolar process In CMOS, the parasitics are worse

CMOS Transistors

Latch-up problem

Preventing Latch-up

ESD protection A very serious problem Not enough theoretical study Many trade secrets Learn from experienced designers