12004 MAPLDReset Circuit Topologies Reference: Analysis of POR Circuit Topologies

22004 MAPLDReset Circuit Topologies Introduction to This Module The seemingly simple issue of FPGA and ASIC power-on reset circuits is nevertheless often a frequent cause of problems. The discussion in this module will cover both the key issues and a variety of circuits, analyzing their strong and weak points. The discussion will in most cases be general logic design but will deal with some particular issues with Field Programmable Gate Arrays (FPGAs).

32004 MAPLDReset Circuit Topologies Analysis Assumptions 1.The external POR circuitry is properly designed. This is not always a valid assumption as there have been many "wacky" implementations of power-on reset circuits. Design of these circuits is outside the scope of this application note. 2.The clock is generated by a crystal clock oscillator. One of the important characteristics of these devices is their response during the turn-on transient, mainly that they take a certain amount of time to start and then become stable. Additionally, the oscillator may not start clean. 3.The clock is not gated off. If that is not true, such as when areas of the circuit where the clock is gated off for power savings, then additional issues arise. 4.The POR signal is asynchronous to CLK. 5.The period of CLK is large compared with the metastable state resolution time of the flip- flop being used for synchronization. 6.The POR assertion time exceeds the clock oscillator and FPGA start times. 7.The output of the internal POR circuit drives the asynchronous set/reset of flip-flops (alternatively it may be pipelined, which is another distinct case). Since modern FPGAs all have asynchronous flip-flop inputs, this is often used to save logic resources, delay, and power. This is an important consideration since these inputs, unlike D's and ENABLE's, are sensitive to glitches. It is further assumed that timing specifications are met for set/reset distribution including the "removal" time. 8.Noise pulses on the input POR signal is a credible situation.

42004 MAPLDReset Circuit Topologies Analysis 7 Assumption Unintended operation or lockup of finite state machines or systems may result if: · The flip-flops come out of reset during different clock periods. · Sets of finite state machines do not come out of reset during the same clock period. · The reset signal is removed from the flip-flops asynchronous set/preset as there is the potential for one or more uncontrolled metastable states if the clock is running. Therefore, only reset circuits that [attempt to] remove power-on reset synchronously (PORS) will be discussed.

52004 MAPLDReset Circuit Topologies Field Problems A significant problem with many power-on reset circuits is that the designers often implement a favored circuit without first establishing the true system requirements and then analyzing the circuit performance to those requirements, particularly under transient or anomalous conditions. As one example, many power- on reset signals are reliable when bringing the logic on-line after the application of power. However, many circuits that have been examined have shown poor performance during the turn-off transient, which is critical to protect the contents of devices such as EEPROMs. This module will only deal with power-on circuits and does not handle the power-off transient condition.

62004 MAPLDReset Circuit Topologies System Issues None of the circuits discussed in this module are intended to deal with issues of logic devices not starting (e.g., following their truth table) instantly after the application of power. These system-level issues, based on system-level requirements, must be analyzed and, if necessary, dealt with at the system level and not at the logic level internal to the FPGA or ASIC. Significant issues related to the analysis and selection of a power- on reset circuit for a particular application include: –Dependence on clock signal being operational –Noise immunity –Critical timing path impact

72004 MAPLDReset Circuit Topologies Figure 1A Discuss

82004 MAPLDReset Circuit Topologies Figure 1A Fully synchronous Delays –Delay for oscillator to start (10’s of ms) –But for FPGAs, there’s a delay for FPGA to start, load, release outputs, etc. Rejects noise that is not coincident with clock edge –External analog filters can help; device input transition times must be met, simple RC circuits may violate timing constraints –Internal digital FSM can act as a filter, care must be taken for startup conditions, latency, timing, metastable states, etc. –No general solution since noise can be arbitrarily large in time

92004 MAPLDReset Circuit Topologies Figure 1B Discuss

MAPLDReset Circuit Topologies Figure 1B Designer’s intent on this circuit was to filter out noise on the PORS* line. Note that short pulses coming in can result in a static hazard output on PORS*

MAPLDReset Circuit Topologies Figure 1C Discuss

MAPLDReset Circuit Topologies Figure 1C Fixes static hazard problem for narrow noise spikes. Only one input at a time changes to the OR gate (or mux, LUT, etc.).

MAPLDReset Circuit Topologies Asynchronously Applied, Synchronously Removed Circuits Remember, many programmable logic devices will not allow inputs in or outputs out until the device starts.

MAPLDReset Circuit Topologies Figure 2 Discuss

MAPLDReset Circuit Topologies Figure 2 POR* wrapped around the synchronizing flip-flops to asynchronously assert PORS* –Applied prior to clock start time Removal is clean since properly sync’d to FFA and FFB FPGA start time may make the asynchronous application of POR* appear to take action and give a false sense of security to the designer and reviewer for a critical application. –Schematic, or its VHDL equivalent, does not capture the electrical characteristics of the device during the turn-on transient. Noise or runt pulses will get onto the reset network, resulting in incomplete resets and metastable states. The logic gate slows the signal down relative to Figure 1.

MAPLDReset Circuit Topologies Figure 3 Discuss

MAPLDReset Circuit Topologies Figure 3 Fixes some of the problems of Figure 2. No combinational path; needs a clock. Transients can be caught by FFA and then cleaned up. Is this bulletproof for a short run pulse?

MAPLDReset Circuit Topologies Figure 4A Discuss

MAPLDReset Circuit Topologies Figure 4A POR* can be distributed prior to the clock starting. Note that the FPGA must be fully operational too, as discussed above. FFB will take care of any metastability on the PORA* signal. Noisy glitches are reasonably well handled. –FFA and FFB should be hand placed to minimize POR* skew. –Runt pulses on POR* are not bulletproof. Is FFB reliable with POR* removed asynchronously? Note that some aerospace flip-flops are built with TMR structures. Other flip-flops may internally “glitch” or have a hazard and not be stable. –For SX-S circuits, analysis and SPICE simulations have shown that the clear may be asynchronously removed if the D=0.

MAPLDReset Circuit Topologies Figure 4B Discuss

MAPLDReset Circuit Topologies Figure 4B Extension of the circuit shown in 4A. Longer reset after detection of a transient.

MAPLDReset Circuit Topologies Notes and References 1."Some Characteristics of Crystal Clock Oscillators During the Turn-On Transient." This application note discusses and shows what the output of an oscillator may be during the turn-on transient. Examples shows include runt pulses of various sizes and polarities. 2."Asynchronous & Synchronous Reset Design Techniques - Part Deux“ 3."Small Explorer WIRE Failure Investigation Report." This is Appendix F of the WIRE Mishap Investigation Board Report, June 8, "Startup Transient," from Advanced Design: Designing for Reliability, 2001 MAPLD International Conference, Laurel, MD, September 10, "Current Radiation Issues for Programmable Elements and Devices," IEEE Transactions on Nuclear Science, December "RH1020 Single Event Clock Upset Summary Report," Richard B. Katz and J. J. Wang, March 5, Thanks to Melanie Berg of Ball for the helpful comments and suggesting to add notes about the extra delay in the reset path when using topologies such as those shown in Figure 2. 8."Hazard Analysis," from Design Guidelines and Criteria for Space Flight Digital Electronics. and 9.Timing Analysis of Asynchronous Signals