MicroComputer Engineering DigitalCircuits slide 1 Combinational circuits Changes at inputs propagate at logic speed to outputs Not clocked No internal state (memoryless)

MicroComputer Engineering DigitalCircuits slide 2 Example I O 11 & & I2 I1 I0 O 1

MicroComputer Engineering DigitalCircuits slide 3 NOT combinational & & S R - latch (has a state) D Q D - flip-flop (clocked, no path)

MicroComputer Engineering DigitalCircuits slide 4 Combinational logic can be connected into sequences - can be connected parallel 1111 & 1

MicroComputer Engineering DigitalCircuits slide 5 Combinatorial loop This is OK: But what is this? 1 1 1

MicroComputer Engineering DigitalCircuits slide 6 Combinationial loop Impossible! Logical nonsense Electrical trouble

MicroComputer Engineering DigitalCircuits slide 7 Combinational loop This is a “combinational loop” We must never have, or form, a combinational loop

MicroComputer Engineering DigitalCircuits slide 8 How is this usually solved? D Q “The edge-triggered flip-flop!”

MicroComputer Engineering DigitalCircuits slide 9 The edge-triggered flip-flop! Never a combinational path from in to out A memory device, holds the value of “Q” until “clocked” Ignores the value at “in” until “clocked” D Q in out

MicroComputer Engineering DigitalCircuits slide 10 Beginners explanation Flipflop “samples” its input at the rising edge and presents that value on the output. D Q t clock 1 0 A “rising edge” A “falling edge”

MicroComputer Engineering DigitalCircuits slide 11 Flip flops in the circuit We will put flip flops in our circuit (Good for “breaking” combinational loops) and clock them all with the same clock D Q

MicroComputer Engineering DigitalCircuits slide 12 Setup time, t setup t he time the D input must be stable before the rising edge of the flip-flop. Hold time, t hold t he time the D input must be stable after the rising edge of the clock If the setup or hold time parameters are violated the Q output will be either logic 0, logic 1 or the flip-flop will enter a metastable state, but will eventually become a valid logic level. setup t hold t 1, 0 or metastable! D Clk Q Timing of a positive edge triggered D flip-flop

MicroComputer Engineering DigitalCircuits slide 13 Clock to output delay pLH(CQ) t pHL(CQ) t setup t hold t 1, 0 or metastable! D Clk Q Clock-to-output delay, t p The delay of a low to high transition and the delay of a high to low transition may be different.

MicroComputer Engineering DigitalCircuits slide 14 Example 1 BAD OK D Q 1 Suppose the flip flop holds a “1”. Let’s clock this circuit...

MicroComputer Engineering DigitalCircuits slide 15 Example D Q Holding Clock “pulse” one “clock cycle”

MicroComputer Engineering DigitalCircuits slide 16 Example D Q Samples the “0”

MicroComputer Engineering DigitalCircuits slide 17 Example D Q The exact instant that the output changes!

MicroComputer Engineering DigitalCircuits slide 18 Example D Q the circuit becomes stable again A very short time later... Called a logic “delay” (Propagation through the combinational logic)

MicroComputer Engineering DigitalCircuits slide 19 Example D Q until the next clocking And it stays like that....

MicroComputer Engineering DigitalCircuits slide 20 Combinational logic in the MIPS Zero extend box Sign extend box Controllable sign/zero extend box “Tap box” (pick out fields of bits) Shift left two bits

MicroComputer Engineering DigitalCircuits slide 21 Zero extend box 16 In[0..15] Out[16..31] Out[0..15] 16 zeroes !

MicroComputer Engineering DigitalCircuits slide 22 Sign extend box 16 In[0..15] Out[16..31] Out[0..15] In[15] copied 16 times

MicroComputer Engineering DigitalCircuits slide 23 Controllable zero / sign extend box 16 In[0..15] Out[16..31] Out[0..15] In[15] & Control

MicroComputer Engineering DigitalCircuits slide 24 Tap box Contains no logic circuits Regroup input bits Opcode field Instruction Rs field Rt field Rd field Immediate field

MicroComputer Engineering DigitalCircuits slide 25 Shift left two bits 32 Out bit [2..31*] In bit [0..31] Out bit 1 Out bit * Two bits lost

MicroComputer Engineering DigitalCircuits slide 26 Arbitrary logic Given a truth table: A B C D X Y Z Digital design Logic ABCDABCD XYZXYZ

MicroComputer Engineering DigitalCircuits slide 27 So, it’s enough just to have the truth table..... We have tools to build the “logic box” “Logic synthesis”

MicroComputer Engineering DigitalCircuits slide 28 The multiplexor Special truth table: A B Cont Out Easy to generalise to “A, B, C, D....” A B Cont Out

MicroComputer Engineering DigitalCircuits slide 29 Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend msblsb"0" msblsb"0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

MicroComputer Engineering DigitalCircuits slide 30 Example: 4 bit Logical Right Shifter If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs) A0A1A2A3 S0 S1 ”0”

MicroComputer Engineering DigitalCircuits slide 31 Example: 4 bit logical Right Shifter II Shift two bits right A0A1A2A3 S0 = 0 S1 = 1 ”0” A0A1 A2A3 A2A3 ”0”

MicroComputer Engineering DigitalCircuits slide 32 Example: 4 bit Right Shifter III If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs) A0A1A2A3 S0 = 0 S1 = 1 ”0” A0A1 A2A3 A2 A3 ”0” A2 A3”0”

MicroComputer Engineering DigitalCircuits slide 33 General Shift Right Scheme 16 bit using MUXes If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs)

MicroComputer Engineering DigitalCircuits slide 34 Barrel Shifter (remember?) Technology-dependent solutions: 1 transistor per switch:

MicroComputer Engineering DigitalCircuits slide 35 What about adders? A[0] A[1].... A[31] B[0] B[31]C[0] C[1].... C[31] Impractical to represent by truth table Exponential in number of input bits 32 A B C+

MicroComputer Engineering DigitalCircuits slide 36 Adders are special..... We’ll talk about them later Also, multipliers Let’s just assume they exist

MicroComputer Engineering DigitalCircuits slide 37 Subtract ? A - B ? = A + NOT (B) + 1 Yes, there’s an easier way A B 1 + +

MicroComputer Engineering DigitalCircuits slide 38 Controllable Add / Sub ? Subtract Add Choose ABAB

MicroComputer Engineering DigitalCircuits slide 39 How it’s really done 32 =1 32 A B Choose Carry in +

MicroComputer Engineering DigitalCircuits slide 40 What’s the point of this ? The ALU is combinational Must have control signals to choose! 32 ALU Control points

MicroComputer Engineering DigitalCircuits slide bit wide inverter ? In bit[31] In bit[30] In bit[1] In bit[0] Out bit[31] Out bit[30] Out bit[1] Out bit[0] Easier to draw!

MicroComputer Engineering DigitalCircuits slide 42 Same idea : 32 - bit wide multiplexors 32 - bit wide clocked registers, such as the –Program counter –write back data register D Q 32 Clock signal not drawn

MicroComputer Engineering DigitalCircuits slide 43 Memories ? Register file Instruction memory Data memory We’ll treat these as combinational (not “clocked”)