Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT2 will be reviewed. We will review the following logic families: Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic 4/25/2017

A brief introduction to Dynamic logic Steady-State Behavior of Dynamic Logic Performance of Dynamic Logic Noise Considerations in Dynamic Design 4/25/2017

Dynamic Latch: Charge Leakage Stored charge leaks away due to reverse-bias current. Stored value is good for about 1 ms. Value must be rewritten to be valid. If not loaded every cycle, otherwise it must be ensured that the latch is loaded often enough to keep data valid. Cd+Cg X 4/25/2017

Dynamic Latch-Operation Uses complementary transmission gate to ensure that storage node is always strongly driven. Latch is transparent when transmission gate is closed. Storage capacitance comes primarily from transmission gate diffusion capacitance and inverter gate capacitance.  = 0: transmission gate is off, inverter output is determined by storage node.  = 1: transmission gate is on, inverter output follows D input. Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid. 4/25/2017

Dynamic Combinational Logic Precharge/ Evaluate Networks M p e V DD PDN f In 1 2 3 Out PUN C L network n 4/25/2017

Example of Dynamic Circuit OUTPUT A C B CLK CLK OUTPUT Precharge Evaluation Precharge 4/25/2017

General Concept Precharge and Evaluation Mp precharge transistor OUTPUT A C B CLK ф Me Evaluation transistor CLK OUTPUT Precharge Evaluation Precharge Example of nmos block For OUTPUT= (A.B + C)’ 4/25/2017

Charge and discharge Clock, ф A B C Output 4/25/2017

Overcoming the charge leakage and the charge sharing Mp OUTPUT A C B CLK ф Me 4/25/2017

Example… continue V f M • N + 1 Transistors Out • Ratioless DD f M p • N + 1 Transistors Out • Ratioless • No Static Power Consumption A • Noise Margins small (NM ) L C • Requires Clock B f M e 4/25/2017

Charge Leakage Solution: Make CL small by reducing the drain Cd and Gate Cg capacitance small. 4/25/2017

Charge Sharing To Reduce Charge Sharing Increase Cout Reduce Cg of input transistors Use feedback transistor at the output 4/25/2017

Clock Feed through Solution: Make contacts to the substrate: to Gnd, Vdd to take away the injected electrons 4/25/2017

Cascading Dynamic Logic 4/25/2017

Transient Response 6.0 f V 4.0 ) PRECHARGE l t EVALUATION o V ( t u o out 4.0 ) PRECHARGE l t EVALUATION o V ( t u o V 2.0 0.0 0.00e+00 2.00e-09 4.00e-09 6.00e-09 t (nsec) 4/25/2017

4 Input NAND VDD Out f GND In1 In2 In3 In4 4/25/2017 Prentice Hall/Rabaey

Dynamic Flip-Flop D Q F X Y x 4/25/2017

P-E logic Instead of using a static invert to ensure that 0 to 1 transitions occur during precharge, we can exploit the duality between n- block and p-block . The precharge output value of n- block equals 1, which is the correct value for the input of a p-block during precharge. All PMOS transistors of the Pull-Up Network (PUN) are turned off, so, an erroneous discharge at the on set of the evaluation phase is prevented. In a similar way, an n- block can follow a p-block without any problem, as the precharge value of inputs equals 0. To make the evaluation and precharge times of the p and n-block coincide, one has to clock the p-block with an inverted clock p’. 4/25/2017

PE Logic M p e V DD PDN f In 1 2 3 Out PUN C L network n 4/25/2017

Domino logic A Domino logic module consists of a n block followed by a static inverter. This ensures that all inputs to the next logic block are set to 0 after the precharge periods. Hence, the only possible transition during the evaluation period is 0 to 1 transition, so that formulated rule is obeyed. 4/25/2017

The block of Domino logic 4/25/2017

One Bit full Adder-Domino 4/25/2017

Simulation Results 4/25/2017

2-Phase Logic We can use two-phase clock to control logic transition similar to PE. A single clock (phi1 or phi2) is used to precharge and evaluate the logic block. The succeeding stage is operated on the opposite clock phase. A latch is needed between two stages. 4/25/2017

2-Phase logic Ф1’ ф1’ Ф2’ To ф1 stage From ф2 stage 4/25/2017 ф1 ф2 n-logic ф2 Ф1’ ф1’ Ф2’ To ф1 stage From ф2 stage 4/25/2017

2-Phase Domino logic 4/25/2017

Multiple O/P Domino Logic The main concept behind MODL is the utilization of sub-functions available in the logic tree of domino gates, thus saving replication of circuitry. The additional ouputs are obtained by adding precharge devices and static inverters at the corresponding intermediate nodes of the logic tree. 4/25/2017

Multiple output Domino 4/25/2017

MODL 4-bit Carry Block C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 G 1 + P 2 P 1 C o C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 +P 3 P 2 P 1 C 0 C 4 = G 4 + P 4 G 3 + P 4 P 3 G 2 +P 4 P 3 P 2 G 1 + P 4 P 3 P 2 P 1 C 0 4/25/2017

CMOS2 Logic In Ф’ ф Out 4/25/2017

CMOS2 and Domino Logic CMOS2 Latch/INV Latch/INV Domino Logic N BLOCK F’ CLK’ CLK’ A’ D’ N BLOCK F CLK A’ CLK B’ C’ A CLK’ B C’ D’ B’ C’ D’ CMOS2 Latch/INV Latch/INV Domino Logic 4/25/2017

F’ = (AB + BC + D)’ = (A’ + B’)(B’ + C’)D’ = D’(A’C’ + B’) Example of CMOS2 Logic F = AB + BC + D, F’ = (AB + BC + D)’ = (A’ + B’)(B’ + C’)D’ = D’(A’C’ + B’) CLK’ F CLK F’ B’ C’ D’ A’ A 4/25/2017

NORA Logic Combining C2MOS pipeline register and P-E CMOS dynamic logic function block, we get NORA-CMOS (mean NO-Race). The method is suitable for the implementation of pipelined datapaths. 4/25/2017

The block of NORA logic 4/25/2017

Cascode Logic Further refinement leads to a clocked version of the CVSL gate. This is really just two “Domino” gates operating on the true and complement inputs with a minimized logic tree. The advantage of this style of logic over domino logic is the ability to generate any logic expression, making it a complete logic family. This is achieved at the expense of the extra routing, active area, and complexity associated with dealing-rail logic. 4/25/2017

CASCOD Logic 4/25/2017

A clocked version of the CVSL gate 4/25/2017

The block of 8-bit DRCA using the Cascode logic 4/25/2017

Comparison of 8-bit Adders Designed with Dynamic Logic Seven circuits using six dynamic logic functions are designed and simulated. The performance in terms of power, area, delay, energy and AT2 are compared. 4/25/2017

Dynamic Logic Adders that are designed and compared Domino logic 8-bit Adder P-E logic 8-bit Adder NORA logic 8-bit Adder 2-Phase Logic 8-bit Adder Multiple O/P Domino Logic 8-bit Adder Cascode Logic 8-bit Adder 4/25/2017

Power 4/25/2017

Area 4/25/2017

Delay 4/25/2017

DP 4/25/2017

AT2 4/25/2017

Conclusion Domino Logic: It has minimum area and number of transistors. The power consumption is low, and the delay is the longest. The DP and AT2 are average. If the design goal is minimum area and speed is a secondary concern the Domino logic is the best structure for Ripple Carry Adder. 4/25/2017

Conclusion…. P-E Logic: has a small area and the minimum number of transistors. The power consumption is low, and the delay is short. It has the lower DP and AT2 for Ripple Carry Adder. If the logic has no inherent race problem, it will be the best choice for Ripple Carry Adder. 4/25/2017

Conclusion…. P-E (race-free) Logic: In order to avoid the race condition of P-E Logic, the P-E (race-free) Logic is introduced. It has a small area and average of number of the transistors. The area and number of transistors is larger than P-E logic. The power consumption is average. The delay is shortest. It has lower DP and AT2 for Ripple Carry Adder. For synthesis, it is the best choice for Ripple Carry Adder. 4/25/2017

Conclusion…. NORA Logic: The power consumption is higher. The area is small, and using a few transistors except Domino logic. The delay is longer. The DP is high and AT2 are average. 4/25/2017

Conclusion…. 2-Phase Logic: The area is larger and the number of transistors is more than others except Cascode logic. The delay is longer. The power consumption, DP and AT2 are extremely high. Try to avoid this logic structure for designing Ripple Carry Adder. 4/25/2017

Ф1 Ф2 block 4/25/2017 Ф1’ ф2’ ф1 ф2’ From ф2 To ф1 stages stage Ф1’ ф2 Ф1’ ф2’ ф1 ф2’ From ф2 To ф1 stages stage Ф1’ ф2 Ф Ф1’ ф2’ Ф1 block Ф2 block 4/25/2017

2-phase domino logic 4/25/2017

Dynamic Circuits: Advantages & Disadvantages Circuits occupy less area the static circuits Operate at higher speed than static CMOS Noise sensitive Drawbacks: Affected by charge sharing and charge re- distribution Always require clocks Cannot operate at low frequency Design is not straight forward 4/25/2017

Race Condition of PE device 4/25/2017