Presenter: Shao-Chieh Hou International Database Engineering & Application Symposium (IDEAS’05)

It is a challenge to debug the software and hardware in the SOC for that neither the software nor the hardware is error-free. By combining the emulator and the simulator, with the new software debug engine, the new bus status monitor, and the new checkpoint technology, the high speed, easy-used software/hardware co-debugging environment is presented in this paper.

The SoC Design become complex  Consists 。 Microprocessor 。 Memory 。 Another IP 。 Software Time-to-market  Integrate both software and hardware as soon as possible In this way, the SW/HW co-debug environment is needed

This paper JHDL debugger environment[1]-[3] JTAG use in debug[4]-[6] Processor-base debug and bus monitor[5] Software debug with JTAG[6] SW debug engine[7] Snapshot technology use in hardware debug[8][9] Hardware Software HDL select Data output Internal data get

Goal: signal step, breakpoint, register modify => Data output /command input => Command decoder => Achieve the goal => Register modify and monitor => Run-Length encoder JTAG:30MHZ Bandwidth:2.0875MB/s

Goal: monitor the bus status (both system bus and memory bus), and save data into a block- RAM => Bus status collect => Compress the bus status => Data output /command input => Control memory access

Goal: monitor other IP and signal in SoC Scan cell for signal trace Scan cell control Signal capture and compress Embedded logic analyzer control

Software:  Read register  Breakpoint  Step run Hardware:  Bus monitor  Scan chain 32-bit REX CPU(100MIPS) Co-debug by match both HW signal and SW values

The paper give a good idea for “what the co- debug need both in SW and HW” The paper idea is similar to our co-debug environment The paper is lack of experimental result and detailed, but the main idea is useful in SW/HW co-debug.