Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

Overview  Project Overview  Introduction  Background  Design Specifications  Preliminary Design  Simulation  Conclusion  Project Overview  Introduction  Background  Design Specifications  Preliminary Design  Simulation  Conclusion 2

Project Overview Tim Murphy 3

Introduction  Clock simulation  Closed-loop position  Tracking a stepped input  Clock simulation  Closed-loop position  Tracking a stepped input 4

Background 5

Design Specifications  Time domain specifications:  Settling time: < 0.5 seconds  Percent overshoot: < 10%  Zero steady-state error  Variation of a PID controller  Time domain specifications:  Settling time: < 0.5 seconds  Percent overshoot: < 10%  Zero steady-state error  Variation of a PID controller 6

Preliminary Design Jenn Transue 7

Preliminary Design  Response to a step input  Uncompensated System  Proportional (P) Controller  Proportional Derivative (PD) Controller  Response to a step input  Uncompensated System  Proportional (P) Controller  Proportional Derivative (PD) Controller 8

Preliminary Design – Uncompensated  Uncompensated closed-loop system:  54.6% overshoot  1.01 second settling time  Zero steady-state error  Uncompensated closed-loop system:  54.6% overshoot  1.01 second settling time  Zero steady-state error 9

Preliminary Design – P Controller  Root Locus Analysis:  10% Overshoot  K P =  Root Locus Analysis:  10% Overshoot  K P =

Preliminary Design – P Controller  Compensated closed-loop system:  K p =  9.97% overshoot  0.94 second settling time  Zero steady-state error  Cannot meet settling time specification  Compensated closed-loop system:  K p =  9.97% overshoot  0.94 second settling time  Zero steady-state error  Cannot meet settling time specification 11

Preliminary Design – PD Controller 12

Preliminary Design – PD Controller  Adjusted overshoot specification in calculations  Compensated closed-loop system:  K p =  K d =  10% overshoot  second settling time  Zero steady-state error  Do not need an integral component  Adjusted overshoot specification in calculations  Compensated closed-loop system:  K p =  K d =  10% overshoot  second settling time  Zero steady-state error  Do not need an integral component 13

Simulation Jacob Medinilla 14

Simulation – Pole-Zero Plot  Compensated closed-loop system  Stable  Relatively fast system  Compensated closed-loop system  Stable  Relatively fast system 15

Simulation – Model Compensated System Response to Stepped Input 16

Simulation – Results Compensated System Response to Stepped Input 17

Conclusion – Expected Challenges  Design not validated  Potential for unexpected behavior  Sensitivity to controller tuning  Possibility erroneous values from previous labs  Design not validated  Potential for unexpected behavior  Sensitivity to controller tuning  Possibility erroneous values from previous labs 18

Conclusion – Schematic 19

Summary  Uncompensated System cannot meet specifications  Proportional Controller cannot meet specifications  PD Controller required  K p =  K d =  Will need to adjust gains to achieve specifications in lab  Uncompensated System cannot meet specifications  Proportional Controller cannot meet specifications  PD Controller required  K p =  K d =  Will need to adjust gains to achieve specifications in lab 20

Questions? 21