Why segregate blocking and non-blocking assignments to separate always blocks? always blocks start when triggered and scan their statements sequentially.

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Why segregate blocking and non-blocking assignments to separate always blocks? always blocks start when triggered and scan their statements sequentially.

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Why segregate blocking and non-blocking assignments to separate always blocks? always blocks start when triggered and scan their statements sequentially Blocking assignment: = (completes assignment before next statement executes) Non-blocking: <= (all such statements complete at once at end of the always block)

A mixed always block for a funny shifter module funnyshifter (input data, clk, output reg [3:0] yout); reg [3:0] asig; initial asig = 4'b0000; (posedge clk) begin asig[1] = asig[0];// Value of asig(0) on entry written to asig(1) at // end of loop - D-ff asig[2] = asig[1];// Value of asig(1) as step written is already // updated so asig(2) = asig(0) at end of loop asig[3] = asig[2];// Value of asig(2) as step written is already // updated so asig(3) = asig(0) at end of loop asig[0] = data;// asig(0) = data at end of loop - D-ff yout[3:1] <= asig[3:1];// non-blocking unambiguous D-ff's yout[0] <= data; end endmodule

Simulation results for different order of statements Result with first statement order: asig[3:1] are redundant Swap first and third lines and there is a double shift register

Same mixed always block but different statement order - designer’s probable intention module funnyshifter (input data, clk, output reg [3:0] yout); reg [3:0] asig; initial asig = 4'b0000; (posedge clk) begin asig[3] = asig[2];// Value of asig(0) on entry written to asig(1) at // end of loop - D-ff asig[2] = asig[1];// Value of asig(1) as step written is already // updated so asig(2) = asig(0) at end of loop asig[1] = asig[0];// Value of asig(2) as step written is already // updated so asig(3) = asig(0) at end of loop asig[0] = data;// asig(0) = data at end of loop - D-ff yout[3:1] <= asig[3:1];// non-blocking unambiguous D-ff's yout[0] <= data; end endmodule

The right way to do it: module funnyshifter (input data, clk, output reg [3:0] yout); reg [3:0] asig; initial asig = 4'b0000;// Note: this line initializes only the simulator // and has no effect on hardware. I needed it to generate the // simulator output by starting in a known state. (posedge clk) begin asig <= {asig[2:0], data}; // non-blocking unambiguous D-ff's yout[3:1] <= asig[3:1]; yout[0] <= data; end endmodule

Suggested Rules and Styles “Avoid writing modules that… mix the creation of state… in an posedge block with the definition of the next-state function... (This) sidesteps a tremendous amount of confusion and frustration that result from incorrect use of blocking = versus non-blocking <= assignment.” Dally and Harting, Digital Design a Systems Approach, pp “Two rules are so important this is the only place that you’ll find bold font in this book. Always use blocking assignments (=) in always blocks intended to create combinational logic. Always use non-blocking assignments (<=) in always blocks intended to create registers. Do not mix blocking and non-blocking logic in the same always block.” John F. Wakerly, Digital Design Principles and Practices, pg. 316.