RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors

Introduction F RSIM - the Rice Simulator for ILP Multiprocessors RSIM is a discrete event-driven simulator based on YACSIM library F Purpose Primarily designed to study shared- memory multiprocessor architectures built from state-of-the-art processors

Architecture Features n Processor Microarchitecture n The Cache and Memory System n The Multiprocessor System

Processor features n Multiple instruction issue n Out-of-order (dynamic) scheduling n Register renaming n Static and dynamic branch prediction support n Non-blocking loads and stores n Speculative load execution before address disambiguation of previous stores n Simple and optimized memory consistency implementations

RSIM Processor Microarchitecture

Memory hierarchy features n Two-level cache hierarchy n Multiported and pipelined L1 cache, pipelined L2 cache n Multiple outstanding cache requests n Memory interleaving n Software-controlled non-binding prefetching

Multiprocessor system features n CC-NUMA shared-memory system with directory-based cache-coherence protocol n Support for MSI or MESI coherence protocols n Support for sequential consistency, processor consistency, and release consistency n Wormhole-routed mesh network

The RSIM Memory System

RSIM Implementation n Event-driven simulation library n Processor out-of-order execution engine n Processor memory unit n Cache hierarchy n Directory and memory module n Interconnection system

The RSIM Memory and Network System n Memory hierarchy and Interconnection system n Cache hierarchy n Directory and Memory Simulation n System Interconnects

Memory Hierarchy and Interconnection System

Cache hierarchy n First Level of Cache-L1 u Either write-through with no-write- allocate or write-back with write- allocate n Second level of Cache u Write-back with write-allocate u Maintaining inclusion of L1

Cache coherence Protocol n MSI u An explicit upgrade message is required n MESI u A message to be sent to the directory on elimination of an exclusive line from the L2 cache is required.

Supported Cache Coherence Protocols

Directory and Memory Simulation n The directory is responsible for maintaining the current state of a cache line, serializing accesses to each line, generating and collecting coherence messages, sending replies, and handling race conditions. n The directory coherence protocol used in RSIM relies on cache-to-cache transfers and uses replacement messages

System Interconnects n Node bus u Connects L2 cache, network interface,and the directory/memory modules within node n Network Interface Modules u modules that connect each node’s local bus to the interconnection network n Multiprocessor Interconnection Network u Separates request and reply networks for deadlock -avoidance

Statistics in RSIM n Overall performance statistics n Other processor statistics n Cache, memory, and network statistics