Stored Program A stored-program digital computer is one that keeps its programmed instructions, as well as its data, in read-write, random access memory (RAM).digital computer programmedread-writerandom access memory The idea of the stored-program computer changed all that. By creating an instruction set architecture and detailing the computation as a series of instructions (the program), the machine becomes much more flexible.instruction set architecture computationprogram By treating those instructions in the same way as data, a stored- program machine can easily change the program, and can do so under program control. Once in the computers memory a program will be executed one instruction at a time by repeatedly going through In the vast majority of modern computers, the same memory is used for both data and program instructions. This is known as the stored program concept or sometimes the Von Neumann principle.

Von Neumann Architecture The von Neumann architecture is a design model for a stored-program digital computer that uses a processing unit and a single separate storage structure to hold both instructions and data. digital computerprocessing unitstorage data Memory is used to store both program instructions and data Program instructions are coded data A central processing unit (CPU) gets instructions and/or data from memory, decodes the instructions and then sequentially performs them. A processor fetches instructions and data from a memory, operates on the data, and writes the results back into memory It is named after the mathematician and early computer scientist John von Neumann.mathematiciancomputer scientistJohn von Neumann Such computers implement a universal Turing machine and have a sequential architecture.universal Turing machinesequential architecture.

Von Neumann Components Input Output Memory ALU Control Unit

CPU The processor itself consists of 3 main components: Arithmetic-logic unit (ALU) in which all arithmetic and logic operations are carried out Control unit coordinates the activities taking place in the CPU, memory and peripherals System clock generates clock pulses to step the control unit through its operation Also Registers special storage locations to hold information temporarily

System clock Electronic component It generates electric signals at a fast speed It controls all functions of computer using clock ticks These ticks of system clock are known as clock cycle and speed of CPU The speed at which the CPU executes instructions is called clock speed or clock rate. It generates a continuous sequence of clock pulse to step the control unit through its operations

Registers Is a small high speed memory inside CPU. Used to store temporary results CPU contains the no of registers and has a predefined functions Register size determines how much information it can store The size of register is in bytes A register can be one,two,four or eight byte

CPU Registers Arithmetic logic unit Program Counter (PC) Control Unit Current Instruction Register (CIR) Memory Address Register (MAR ) Status Register (SR) Memory Data Register (MDR) R0 R1 R2 R3 R4 R5 External bus Main Memory The MDR is sometimes known as the memory buffer register (MBR) General purpose registers

Two internal registers –Memory address register (MAR) Specifies the address for the next read or write –Memory buffer register (MBR) Contains data written into memory or receives data read from memory –I/O address register –I/O buffer register

Top-Level Components

Processor Registers User-visible registers –Enable programmer to minimize main- memory references by optimizing register use Control and status registers –Used by processor to control operating of the processor –Used by privileged operating-system routines to control the execution of programs

User-Visible Registers Address Registers –Index Involves adding an index to a base value to get an address –Segment pointer When memory is divided into segments, memory is referenced by a segment and an offset e.g. CS,DS,ES –Stack pointer Points to top of stack Order is Last in first Out (LIFO) E.g. SP,BP,DI,SI

Control and Status Registers Program Counter (PC) –Contains the address of an instruction to be fetched Instruction Register (IR) –Contains the instruction most recently fetched Program Status Word (PSW) –Condition codes –Interrupt enable/disable –Supervisor/user mode Condition Codes or Flags –Bits set by the processor hardware as a result of operations –Examples Positive result Negative result Zero Overflow

Others Registers 1. General Purpose registers: Available to the programmer and referenced in assembly language programs Performing arithmetic functions Some computers there is one general purpose which is accumulator 2. Stack Pointer (SP): Which points to a stack holding return addresses and is accessed when an interrupt or break in sequential program 3. Current instruction register (CIR): contain both the operator and operand of the current instruction

Working of Registers There are several steps in the Fetch Execute cycle that are executed in order. The CPU goes through this cycle once for each instruction that is executed. To start off the fetch cycle, the address which is stored in the program counter (PC) is transferred to the memory address register (MAR).

Working of Registers To finish the cycle, the newly fetched instruction is transferred to the instruction register (IR) and unless told otherwise, the CU increments the PC to point to the next address location in memory.

Working of Registers The CPU then transfers the instruction located at the address stored in the MAR to the memory buffer register (MBR) via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the control unit (CU). The CPU then transfers the instruction located at the address stored in the MAR to the memory buffer register (MBR) via the data lines connecting the CPU to memory.

CU Operations Fetch : fetches the instruction from main memory Decode: translate the program instruction into commands that the computer can process Execution: control the execution of instruction

Machine Cycle Fetch Instruction Decode Instruction Execute instruction Storing Process of writing the result to the memory is called storing

Control unitALU Registers Instruction cycle in Processor (1) Fetch (2) Decode(3) Execute (4) Store Memory I-timeE-time

How the CPU registers are used Fetch phase : The address of next instruction is copied from the PC to the MAR. The instruction held at that address is copied to the MDR The contents of the MDR are copied to the CIR Execute Phase : The instruction held in the CIR is decoded. The instruction is executed.

Fetch Execute Cycle Start Any instructions to execute? Fetch next instruction Decode instruction Execute instruction Any interrupts to be processed ? Transfer control to interrupt handling program Yes No Yes No

Parallel Processors Parallel processing is the ability of a computer system to undertake more than one task simultaneously. Multiple processing elements in the system Need parallel programming to fully exploit such architectures. To achieve highest efficiency, the program characteristics must match the underlying architecture. Newer computers no longer use the von Neumann architecture

Application of parallel processor Supercomputers utilizing parallel processing are used to maintain the safety. Scientists are using parallel processing to design computer-generated models of vehicles. Airlines use parallel processing to process customer information, forecast demand and decide what fares to charge. The medical community uses parallel processing supercomputers.

Advantages and disadvantages Advantages: –Memory is scalable with number of processors. Increase the number of processors and the size of memory increases proportionately. –Each processor can rapidly access its own memory without interference and without the overhead incurred with trying to maintain cache –Cost effectiveness: can use commodity, off-the-shelf processors and networking Disadvantages: –The programmer is responsible for the details associated with data communication. –It may be difficult to map existing data structures, based on global memory, to this memory organization.