RD53 IP WG 1 Jorgen Christiansen / PH-ESE

IP WG agenda General Issues IP block matrix (no recent changes) General schedule Specifications of IP blocks IP review panel Synergy with other projects Feedback/Status/Requests from IP groups Round table AOB 2

IP block matrix We now have a clear IP block matrix: ~30 IPs We have a few cases with multiple groups working on the “same” IP Monitoring ADC: Bari, CPPM, CERN Bandgap: CPPM, Pavia/Bergamo, CERN Radiation monitor: CPPM, Torino ?. Best (performance/size/power) and sufficient rad hard will be chosen for final designs IPs with no group assignment New: Power-on reset Some IPs that we do not yet know if will be needed (on hold) Special digital library/cells: Size, power, radiation tolerance. VCO for fine time stamping IO PAD TSV (TSMC have TSV but we can most likely not get access) Soft IPs Part of IP WG, IO WG or global pixel chip design/architecture ? Not urgent but needs to define strategy. More IPs may come Optimized electrical link driver – receiver with cable equalization/compensation: ~1Gbits/s Other ? 3

4 CountryDE FRNLIT - INFNUSFRUKUSCZComments Group Bonn CERN CPPM NIKHEF Bari Pav/ Berg (Milano ) Padova Pisa Torino LBNL LPNHE RAL Santa Cruz (Prague ) ANALOG: Coordination with analog WG Temperature sensor. O (P) Radiation sensor O (P) O 2 groups HV leakage current sensor. O (P) Band gap reference OO(P) O 3 Groups Self-biased Rail to Rail analog buffer (P) O MIXED 8 – 12 bit biasing DAC (P) O bit slow ADC for monitoring OO O 3 Groups PLL for clock multiplication O(P) Together High speed serializer ( ~Gbit/s) O(P) (Voltage controlled Oscillator) (P) O Needed ? Clock recovery and jiter filter O(P) Programmable delay O(P) DIGITAL SRAM for pixel region (P) O SRAM/FIFO for EOC. (P) O EPROM/EFUSE (P)O DICE storage cell / config reg (P) O Or TMR ? LP Clock driver/receiver (P) O (Dedicated rad hard digital library) (P) O If needed (compact mini digital library for pixels) (P) O If needed IO: Coordination with IO WG Basic IO cells for radiation (P)O Low speed SLVS driver (<100MHz) (P) O Together High speed SLVS driver (~1Gbits/s) (P) O SLVS receiver (P) O 1Gbits/s drv/rec cable equalizer New C4 and wire bond pads (P)O (IO pad for TSV) O (P) Analog Rail to Rail output buffer O (P) Analog input pad O (P) POWER LDO(s) (P) O Switched capacitor DC/DC (P) O Shunt regulator for serial powering O Power-on reset New Power pads with appropriate ESD (P)O SOFT IP: Coordination with IO WG Control and command interface (P) O Readout interface (E-link ?) (P) O Summary ATLAS/CMS/Neutral ANAACCCCCCAANAAATLASCMSNeutral O's (P)'s

Schedule ~2 years to make IPs. To have full pixel array ROC at end of 3 year RD53 program Who makes what and how: Now Specs of each IP: Q Viable schematic/layout:Q Prototype submission:Q1/ (shared submissions: milestone) Tested Prototype: Q Behavioural modelQ (to allow progress on global pixel) Radiation qualification:Q (2 nd. Prototype)Q (shared submissions: milestone) Final IP:Q Long list of things to deliver for IP (backup slides) 5

Specs of IP blocks We do not yet know what the detailed specs of each IP will be but we have to make first qualified guesses Proposed scheme – schedule 3 months (Q2 2014): Initial specs 1.Initial spec proposal by IP block design group based on our current basic understanding of the global pixel chip specifications and architecture 2.Review of Initial specs within IP working group IP review spec. panel 6 months (Q4 2014) : Specification review/refinement based on initial design work 12 months (Q2 2015): Final specifications 6

IP review panel: Proposal Small panel of assigned “experts” to: Review initial IP specs done by design groups: Q2/ Define/recoomend how to make appropriate IPs:Q Review specs updates: Q4 2014, Q Review designs and test results of IP blocks:2015 Consultancy as needed by different IP design groups: This implies real work for panel members Review panel composition: “Internal experts” 65nm technology Radiation effects IP block generation, integration, database, tools Global pixel chip architecture IP block simulation Analog design Other ? How to get this done for 30 different IPs ?. Grouping of IPs in (~4) families: Analog, IO, PLL/timing/serializer, Digital 4 Review meetings or 2 day IP workshop: June (September) Call for proposals/volunteers ASAP to define panel within next ~4 weeks. First volunteer has emerged. 7

IP synergies Internal RD53 Synergy Common IP design approach and tool integration Exchange of information between RD53 IP design groups WG/RD53 meetings Personnel contacts External Synergy Known HEP/CERN 65nm projects: LPGBT, CMS MPA Other HEP projects may want to migrate quicker than planned to 65nm TSMC (or 130nm TSMC) because of current IBM uncertainties IBM micro-electronics has been put for sale !. Whole community holding its breath and waiting for official news Other ? 8

Backup 9

How to make IPs Group(s) responsible for an IP must deliver everything that makes it a real IP CERN-VCAD design kit / tutorial covers integration aspects of analog and mixed signal IPs in a global digital design IP block repository Data base (Cliosoft) Versioning, who have used what, etc. Basic check of IP blocks (DRC, models, P&R, etc.) Help with IP block generation and use Who ? ( CERN ?) 10

What is needed for an IP ? IP block for integration into large complex mixed signal ASIC Definition and specification of function, performance and interface Design and extensive simulation for conformity with defined specifications across PVT corners, mis-match and radiation effects. Appropriate DRC and verification for use in large pixel chips (e.g. use of layers, power connections, etc.). Prototyping and characterization Radiation testing and qualification. (Synthesis models for basic digital elements) P&R views, Power verification/modeling view Simulation model of IP for chip simulation and verification (PVT-R, loading, timing parameters, mixed signal model, etc.) Documentation. Built in test functions or appropriate scheme to test function when in final chip. Transfer to common IP block repository. Support and possible modifications required to optimize its use/integration in final full scale pixel chips. And probable a few other forgotten points This is a lot more than “just a piece of layout that probably works OK” 11

Common/centralized tasks Coordination of who makes what: Organization Checking/verification of specs: Specification reviews: Organization Definition of how to make IPs: Document and tools setup Follow up on progress: Organization Help and support 65nm tech support IMEC/TSMC/CERN Informal RD53 help: known RD53 colleague and/or 65nm/RD53 mailing list Specific IP help and support: Define specific groups/people for this ?. Radiation effects : Rad WG Layer use verification, P&R, etc.: Top WG Simulation models of IP Digital model Analog behavioral model Mixed signal model Timing models with back annotation based on loading, slew rate,, PVT and radiation corners Power Other ? Common MPW submissions Final IP verification Release review: Organization Common IP repository Database (Cliosoft) Verification: DRC, LVS, simulation model, P&R view,, Access control Tracing of who have gotten what IPs. For what ?. What version ? 12