Analog Capture- Port E

Digital to Analog and Analog to Digital Conversion D/A or DAC and A/D or ADC

Real world (lab) is analog V tt Computer (binary) is digital D/A Conversion ComputerDAC Computer DAC A/D Conversion V

Digital to Analog Conversion (DAC or D/A) 8 bits Computer A/D

Digital to Analog conversion involves transforming the computer’s binary output in 0’s and 1’s (1’s typically = 5.0 volts) into an analog representation of the binary data

D/A conversion can be as simple as a weighted resistor network 4 - bit DAC Converter Resistor values correspond to binary weights of the number D 3 D 2 D 1 D 0, i.e. 1/8, 1/4, 1/2, and 1 Using EWB we can model this device

Analog-to Digital Conversion (ADC or A/D) A/D 8 bits Computer

An ideal A/D converter takes an input analog voltage and converts it to a perfectly linear digital representation of the analog signal If you are using an 8-bit converter, the binary representation is 8-bit binary number which can take on 2 8 or 256 different values. If your voltage range were volts, then 0 VOLTS VOLTS

Voltage (Volts) Analog Voltage LSB

Number of Bits (N)Resolution (1/2 N ) Increment (mV) for 5 volts 61/ / / / / /

Analog signals Analog output is typical of most transducers and sensors. Need to convert these analog signals into a digital representation so the microcontroller can use it. Some characteristics of analog signals. –Maximum and minimum voltages –Precise continuous signals –Rate of voltage change –Frequency if not a steady state signal 12/22/2015 ECE265 11

Analog  Digital Conversion 2-Step Process: Quantizing - breaking down analog value is a set of finite states Encoding - assigning a digital word or number to each state and matching it to the input signal

Step 1: Quantizing Example: You have 0-10V signals. Separate them into a set of discrete states with 1.25V increments. (How did we get 1.25V? See next slide…) Output States Discrete Voltage Ranges (V)

Quantizing The number of possible states that the converter can output is: N=2 n where n is the number of bits in the AD converter Example: For a 3 bit A/D converter, N=2 3 =8. Analog quantization size: Q=(V max -V min )/N = (10V – 0V)/8 = 1.25V

Encoding Here we assign the digital value (binary number) to each state for the computer to read. Output States Output Binary Equivalent

Accuracy of A/D Conversion There are two ways to best improve accuracy of A/D conversion: increasing the resolution which improves the accuracy in measuring the amplitude of the analog signal. increasing the sampling rate which increases the maximum frequency that can be measured.

Resolution Resolution (number of discrete values the converter can produce) = Analog Quantization size (Q) (Q) = Vrange / 2^n, where Vrange is the range of analog voltages which can be represented In our previous example: Q = 1.25V, this is a high resolution. A lower resolution would be if we used a 2-bit converter, then the resolution would be 10/2^2 = 2.50V.

Sampling Rate Frequency at which ADC evaluates analog signal. As we see in the second picture, evaluating the signal more often more accurately depicts the ADC signal.

Aliasing Occurs when the input signal is changing much faster than the sample rate. For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as a 500 Hz (the aliased signal) sine wave. Nyquist Rule: Use a sampling frequency at least twice as high as the maximum frequency in the signal to avoid aliasing.

Overall Better Accuracy Increasing both the sampling rate and the resolution you can obtain better accuracy in your AD signals.

ADC Flow Diagram in HC11 8 channel/bit input V RL = 0 volts V RH = 5 volts Digital input on PE Port E (analog input) Pin: Analog Multiplexer A/D Converter Result Register Interface ADR1 - result 1 ADR2 - result 2 ADR3 - result 3 ADR4 - result 4

Port E and ADR addresses When using Port E as a digital port the port is accessed through address $100A The A/D control register, ADCTL, is at address $1030 The ADR registers are at addresses – these are read only registers. –ADR1 - $1031 –ADR2 - $1032 –ADR3 - $1033 –ADR4 - $ /22/2015 ECE265 23

PE0 AN0 PE1 AN1 PE2 AN2 PE3 AN3 PE4 AN4 PE5 AN5 PE6 AN6 PE7 AN7 ANALOG MUX 8-bits CAPACITIVE DAC WITH SAMPLE AND HOLD SUCCESSIVE APPROXIMATION REGISTER AND CONTROL V RH V RL RESULT REGISTER INTERFACE ADR1ADR2ADR3ADR4 ADCTL A/D CONTROL CCF SCAN MULT CDCCCBCA INTERNAL DATA BUS P 64 M68HC11 Family Data Sheet Stuctural Diagram of ADC on HC11

Output StatesDiscretized Voltage Range Binary Coded Equivalent mV $ mV $ mV $02 …… … V $FF HC11 => 8 bits => 2 8 = 256 HC11 accepts 0 – 5V range Voltage Range = (V RH – V RL )/255 * State

ADCTL register To use the A/D converter on the 68HC11 the users only needs to write to ADCTL for the CPU to read results from the register. There are 8 A/D channels but only 4 results from one of the two groups of 4 can be stored at any one time. –Could also use the 4 registers to save 4 conversions from one input pin ADCTL register – controls how the A/D converter works and how the registers are used. 26

00000 Bit: CCF |No Op| SCAN |MULT | CD | CC | CB | CA CCF: (1) after conversion cycle, (0) when written to. SCAN: Continuous (1) or Not (0) MULT: Multi-Channel (1) or Single Channel (0) 0 = Single Channel is read 4 times CD:CC:CB:CA = 0000 – 0111 Chooses input channel Chooses Channel Group when MULT = ADCTL Register $ Read

Control register continued Bit 7 – is set when the A/D conversion is completed. Writing to ADCTL will clear the bit. Bit 6 – unused Bit 5 – SCAN –Value of 0 – single conversion mode – conversion takes place after a write to the register. –Value of 1 – continuous conversion mode Bit 4 – Multiple/Single Channel Control (MULT) –Value of 0 – Single channel – Consecutive conversions results are stored in consecutive ADRx registers ( single channel converted four consecutive times. –The converted value will be copied in –Value of 1 – each pin in the group is converted and the result stored in the ADR register. The CC control bit determines which group of four channels will be converted. Four sequential channels will be converted one time. 28

Control register continued Bit 3- CD is always clear during normal operation. Bit 2– CC When MULT =1 will select the upper or lower group of eight analog input channels; set = upper group (channels 5-8), clear = Lower group (Channel 1-4). When MULT = 0 CC,CB and CA determine which channel will be converted. (Table 11.10) Bit 1, 0- CB and CA will be ignored when MULT =1.

More on control register The MULT bit says. 1 channel or all 4 Table lists specific group. and pin(s) 30

Example of interface setup What configuration is needed in the ADCTL register for the A/D to convert continuously group 0? Solution: Bits 7 and 6 are don’t cares Bit 5 = 1 convert continuously Bit 4 = 1 group of 4 channels Bits 3 and 2 = 00 group 0, PE0-3 Bits 1 and 0 are not used. Value of xx11 00xx or could store $30 31

Setup example 2 What value needs to be written to the ADCTL register to have continuous conversions of pin PE0? What assembler language instructions would you use to set up this? Set ADCTL as follows: –Bits 7 and 6 – don’t cares –Bit 5 – 1 convert continuously val – –Bit 4 – 0 single channel –Bit 3,2,1,0 – 0000 the value for PE0 The assembler code (assumes A accumulator is free) – LDAA #$20 – STAA $

Example: Enable A/D, select PE0, continuous mode ORG $0200 LDX #$1000 BSET $39,X $80 ; Enable the A/D LDAA #$20; Continous scan, PE0 is selected STAA $30,X conBRA con If only PE0 is connected you will get the converted data in locations $1031-$1034.

Example: Enable A/D, select Group 0 (Channels 1-4), continuous mode ORG $0200 LDX #$1000 BSET $39,X $80 ; Enable the A/D LDAA #$30; continous scan, group 0 is selected STAA $30,X conBRA con If only PE0 is connected you will get the converted data in location $1031.

Options Register $ Bit: ADPU |CSEL | IRQE |DLY | CME | NoOp| CR1 | CR0 ADPU: 0 in this bit disable the A/D, 1 will enable the A/D. CSEL: use internal system clock (1), use E-clock (0) -1

Analog to Digital Results Register: $ $ Bit: ADR2 ($1032) Register $1032 = $02 Options Register ($1039) = $80 ADCTL Register ($1030) = $00 Just read in signal between 19.2 – 39.0 mV on pin E1!