A view on electronics for the prototype of the GOSSIP detector in 0.13um CMOS Technology. Vladimir Gromov Electronics Technology NIKHEF, Amsterdam, the.

Slides:



Advertisements
Similar presentations
MDT-ASD PRR C. Posch30-Aug-02 1 Specifications, Design and Performance   Specifications Functional Analog   Architecture Analog channel Programmable.
Advertisements

Position sensing in a GEM from charge dispersion on a resistive anode Bob Carnegie, Madhu Dixit, Steve Kennedy, Jean-Pierre Martin, Hans Mes, Ernie Neuheimer,
August SGSS front end, Summary August 2008 Edwin Spencer, SCIPP1 SGST Preview SCIPP, UC Santa Cruz Andrey Martchovsky Gregory Horn Edwin Spencer.
5ns Peaking Time Transimpedance Front End Amplifier for the Silicon Pixel Detector in the NA62 Gigatracker E. Martin a,b J. Kaplon b, A. Ceccucci b, P.
NA62 front end Layout in DM option Jan Kaplon/Pierre Jarron.
NA62 front end architecture and performance Jan Kaplon/Pierre Jarron.
A.Kashchuk Muon meeting, CERN Presented by A.Kashchuk.
GOSSIPO-2 chip: a prototype of read-out pixel array featuring high resolution TDC-per-pixel architecture. Vladimir Gromov, Ruud Kluit, Harry van der Graaf.
Timepix2 power pulsing and future developments X. Llopart 17 th March 2011.
14-5 January 2006 Luciano Musa / CERN – PH / ED General Purpose Charge Readout Chip Nikhef, 4-5 January 2006 Outline  Motivations and specifications 
Design of the Front-end Electronics for the GOSSIPO chip. Vladimir Gromov Electronics Technology NIKHEF, Amsterdam, the Netherlands CERN, July the 22 th,
AIDA design review Davide Braga Steve Thomas ASIC Design Group 9 January 2008.
Why silicon detectors? Main characteristics of silicon detectors: Small band gap (E g = 1.12 V)  good resolution in the deposited energy  3.6 eV of deposited.
Performance test of STS demonstrators Anton Lymanets 15 th CBM collaboration meeting, April 12 th, 2010.
Preliminary LumiCAL FEE Specification Presented by Alexander Solin NC PHEP FCAL collaboration meeting, February 12-13, 2006, Krakow (INP PAS),
Pierpaolo Valerio.  CLICpix is a hybrid pixel detector to be used as the CLIC vertex detector  Main features: ◦ small pixel pitch (25 μm), ◦ Simultaneous.
Building blocks 0.18 µm XFAB SOI Calice Meeting - Argonne 2014 CALIIMAX-HEP 18/03/2014 Jean-Baptiste Cizel - Calice meeting Argonne 1.
Gossipo-3: a prototype of a Front-end Pixel Chip for Read-out of Micro-Pattern Gas Detectors. TWEPP-09, Paris, France. September 22, Christoph Brezina.
Fully depleted MAPS: Pegasus and MIMOSA 33 Maciej Kachel, Wojciech Duliński PICSEL group, IPHC Strasbourg 1 For low energy X-ray applications.
Progress on STS CSA chip development E. Atkin Department of Electronics, MEPhI A.Voronin SINP, MSU.
1 Development of the input circuit for GOSSIP vertex detector in 0.13 μm CMOS technology. Vladimir Gromov, Ruud Kluit, Harry van der Graaf. NIKHEF, Amsterdam,
Analog Building Blocks for P326 Gigatracker Front-End Electronics
1 G.Pessina, RICH Elec Upg, 11 April 2010 Analog Channels per chip4 to 8 Digital channel per chip4 to 8 Wire-bond pitch (input channels) Input capacitance.
Using delay lines on a test station for the Muon Chambers Design considerations (A. F. Barbosa, Jul/2003)
Studies of the possibility to use of a Gas Pixel Detector (GPD) as a fast track trigger device George Bashindzhagyan (Speaker,
March 9, 2005 HBD CDR Review 1 HBD Electronics Preamp/cable driver on the detector. –Specification –Schematics –Test result Rest of the electronics chain.
Valerio Re, Massimo Manghisoni Università di Bergamo and INFN, Pavia, Italy Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema Fermi National Accelerator Laboratory.
65 nm CMOS analog front-end for pixel detectors at the HL-LHC
CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC Gianluca Traversi 1,2
LHCb Vertex Detector and Beetle Chip
Fermilab Silicon Strip Readout Chip for BTEV
Pixel detector development: sensor
Tera-Pixel APS for CALICE Progress meeting, 6 th June 2006 Jamie Crooks, Microelectronics/RAL.
Single tube detection efficiency BIS-MDT GARFIELD Simulation GARFIELD Simulation Anode wire voltage as a function of the distance from the wire Electric.
Click to edit Master subtitle style Presented By Mythreyi Nethi HINP16C.
M. TWEPP071 MAPS read-out electronics for Vertex Detectors (ILC) A low power and low signal 4 bit 50 MS/s double sampling pipelined ADC M.
Proposal of a digital-analog RPC front-end for synchronous density particle measure for DHCAL application R.Cardarelli and R.Santonico INFN and University.
Development of a Front-end Pixel Chip for Readout of Micro-Pattern Gas Detectors. Vladimir Gromov, Ruud Kluit, Harry van der Graaf. NIKHEF, Amsterdam,
CERN PH MIC group P. Jarron 07 November 06 GIGATRACKER Meeting Gigatracker Front end based on ultra fast NINO circuit P. Jarron, G. Anelli, F. Anghinolfi,
CBM 12 th Meeting, October 14-18, 2008, Dubna Present status of the first version of NIHAM TRD-FEE analogic CHIP Vasile Catanescu and Mihai Petrovici NIHAM.
R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Gossopo3 3 rd Prototype of a front-end chip for 3D MPGD 1/27/20091GOSSIPPO3 prototype.
Update on works with SiPMs at Pisa Matteo Morrocchi.
Sound Source Location Stand Group 72: Hiroshi Fujii Chase Zhou Bill Wang TA: Katherine O’Kane.
TIMEPIX2 FE STUDIES X. Llopart. Summary of work done During summer I have been looking at a possible front end for Timepix2 The baseline schematic is.
CMOS Analog Design Using All-Region MOSFET Modeling
Front-end Electronic for the CALICE ECAL Physic Prototype Christophe de La Taille Julien Fleury Gisèle Martin-Chassard Front-end Electronic for the CALICE.
Technical status of the Gossipo-3 : starting point for the design of the Timepix-2 March 10, Vladimir Gromov NIKHEF, Amsterdam, the Netherlands.
Pixel structure in Timepix2 : practical limitations June 15, Vladimir Gromov NIKHEF, Amsterdam, the Netherlands.
S.Zucca a,c, L. Gaioni b,c, A. Manazza a,c, M. Manghisoni b,c, L. Ratti a,c V. Re b,c, E. Quartieri a,c, G. Traversi b,c a Università degli Studi di Pavia.
Timing capabilities of Ultra-Fast Silicon Detector 1 A parameterization of time resolution A program to calculate Time resolution UFSD Timing capabilities.
C.Beigbeder, D.Breton, M.El Berni, J.Maalmi, V.Tocut – LAL/In2p3/CNRS L.Leterrier, S. Drouet - LPC/In2p3/CNRS P. Vallerand - GANIL/CNRS/CEA SuperB -Collaboration.
Pixel Sensors for the Mu3e Detector Dirk Wiedner on behalf of Mu3e February Dirk Wiedner PSI 2/15.
P. Name Nikhef Amsterdam Electronics- Technology Vladimir Gromov, NIKHEF, Amsterdam. GOSSIPO-3 Meeting March 31, More on the Preamplifier.
GOSSIPO-3: Measurements on the Prototype of a Read- Out Pixel Chip for Micro- Pattern Gas Detectors André Kruth 1, Christoph Brezina 1, Sinan Celik 2,
A Low-noise Front-end ASIC design based on TOT technique for Read-out of Micro-Pattern Gas Detectors Huaishen Li, Na Wang, Wei Lai, Xiaoshan Jiang 1 State.
R. Kluit Nikhef Amsterdam R. Kluit Nikhef Amsterdam Gossipo3 3 rd Prototype of a front-end chip for 3D MPGD 1/27/20091GOSSIPO3 prototype.
Budker INP V.Aulchenko1,2, L.Shekhtman1,2, V.Zhulanov1,2
STATUS OF SPIROC measurement
M. Manghisoni, L. Ratti Università degli Studi di Pavia INFN Pavia
Valerio Re Università di Bergamo and INFN, Pavia, Italy
DCH FEE STATUS Level 1 Triggered Data Flow FEE Implementation &
Charge sensitive amplifier
L. Ratti, M. Manghisoni Università degli Studi di Pavia INFN Pavia
A Fast Binary Front - End using a Novel Current-Mode Technique
Status of n-XYTER read-out chain at GSI
STATUS OF SKIROC and ECAL FE PCB
BESIII EMC electronics
Readout Electronics for Pixel Sensors
Why silicon detectors? Main characteristics of silicon detectors:
Readout Electronics for Pixel Sensors
Presentation transcript:

A view on electronics for the prototype of the GOSSIP detector in 0.13um CMOS Technology. Vladimir Gromov Electronics Technology NIKHEF, Amsterdam, the Netherlands December the 15 th, 2004

Highlights. Main functionalities of the detector and the principal block diagram of the detector. Main specifications of the electronics.(Single electron efficiency, time resolution, power consumption, analog-to- digital compatibility issue). A choice of sensitive pad-preamplifier coupling in the very front-end (calculation of the parasitic capacitances). Design of the preamplifier in the 0.13um CMOS technology (signal response, noise, hardness to the spread caused by the fabrication process instability). Design of the analog part of the read-out electronics in 0.13um CMOS. Performance of the detector featuring the design (efficiency, signal time-walk, overall time resolution). Block diagram of the DLL-based TDC. Current-steering logic is a way to eliminate switching noise in the mixed analog-digital design. Conclusion.

Preamp Shaper Discriminator Threshold Latch #1 4-bit DLL 1.6ns Latch #2 Latch #16 Preamp Shaper Discriminator Latch #1 Latch #2 Latch #16 to Read-0ut Clock 40MHz Integral circuit in 0.13um CMOS technology Cathode (drift) plane Ingrid Cluster2 Cluster1 Cluster3 Track of the particle Drift distance The principal block diagram of the detector. Z Y X Main functionalities of the device: 1) The pixel structure with a fine pitch (30um …50um) can provide accurate information on X-Y coordinate of each cluster on the track. Thus the projection of the track is seen. 2) With having measured the drift time of each cluster the angle between the track and X-Y plane can be found in order to depict a 3D picture. Design objectives on the read-out electronics: a) the fact that the pixel has been hit needs to be detected with high efficiency and low faulty. The hit should be correctly related to a proper bunch-crossing. b) drift time is to be measured as a latency of the hit arrival time in respect to the bunch-crossing signal accurate enough to determine Z - coordinate of the cluster.

Design objective the desirable vs the possible Main specifications of the electronics: 1)Single electron efficiency (input referred electronic noise). The fluctuations in the number of electrons in a single-electron avalanche is given by: P(n) = 1/M * exp(-n/M), where M is a gas gain factor. With the input referred threshold at the level of 500e inefficiency will be 20% (gas gain M=2000) 10% (gas gain M=4000) 6% (gas gain M=8000). The threshold of 448e corresponds to ENC = 90e RMS 20% 10% Gain=4000 Gain=2000 Gain=8000 Inefficiency Threshold, electrons 448e

2) Time resolution. Both the time resolution of the TDC and the time-walk in the discriminator are independent contributors to the overall time resolution (σ Σ ) of the electronics: σ Σ = √ (σ 2 TDS + σ 2 Time walk ), where σ TDS = ∆t/√12, ∆t – minimum bin size of the TDS σ Time walk is dispersion, related to the time-walk in the discriminator For a 4-bit DLL-based TDC ∆t = 25ns/16 = 1.6ns it yields σ TDS = 0.46ns. The electron drift velocity in the gas is about 20ns/mm therefore the TDC contribution to the overall spatial resolution will be σ spatial TDS = 23um. Under these conditions time walk in the discriminator become the main contributor.

Time-walk. Where does it come from? Signal at the output of discriminator (Sout(t)) is a convolution integral of input current i(t) and pulse response function (H(t)) of the electronics. Low threshold High threshold Time, ns Sout(t) Signals at the input of discriminator, arbitrary unit Range of time- walk for the fast shaped signal Range of time-walk for the slow shaped signal A fast shaped signal A slow shaped signal

i(t) - input current : Ion current occurs in the Micromegas-pad gap in the period ∆t ion = (∆L) 2 /μ U ≈ 30ns, where ∆L ≈ 50um is the Micromegas-pad distance U ≈ 400V is Micromegas-pad voltage μ= 1.72cm 2 V -1 sec -1 is mobility of ions in Argon Single-electron current in the detector st() t St1() Integral of current induced by a single electron. time,ns i(t) electron component ion component 10% is electron contribution to the overall charge 90% is ion contribution to the overall charge

H(t) - shaping function (δ-pulse response) Let us take shaping function of the electronics as follows F(p)=1/[(p  1 + 1) (p 2 +1)]. It demonstrates pulse response f(t,(t,  1  2  ) ft  1  2  () 1  1  2() exp t  1 t  2  ft1  10  () ft8   () t time,ns Pulse response of the electronics (τ1=1ns, τ2=10ns) Pulse response of the electronics (τ1=8ns, τ2=10ns)    

Distribution of the threshold-crossing time. Monte-Carlo simulations Integrals of the distributions  10 4 Entries Gain=2000, Thr = 448e, τ1=1ns, τ2=10ns Gain=2000, Thr = 448e, τ1=8ns, τ2=10ns time,ns Entries Gain=2000, Thr = 448e, τ1=1ns, τ2=10ns Gain=2000, Thr = 448e, τ1=8ns, τ2=10ns inefficiency=20% !!! Fast shaping enables us to get much better time resolution at a given gas gain (threshold).

3) Power consumption. Number of channels per wafer = π D 2 /(4 pitch 2 ) = 3.14 * 10 6 with power consumption 10W/wafer (possible to cool it down by gas flow) !!! Power consumption per channel = 3.2uW 4) Switching noise. In a mixed-mode design switching noise coming from digital part of the circuit back to high sensitive analog front-end is a very important issue. The most most common way to eliminate switching noise is using current-steering logic. Although it reduces speed and increase static power consumption. D=10cm pitch =50um

Preamp Ingrid Preamp i(t) C1 C2 C3 C0 ~ 20pF R0 U1=-300V…-400V C4 R4 -800V Cathode (drift) plane R1 The very front-end. DC or AC coupling to the Preamp.

The very front-end. DC or AC coupling to the Preamp. Safety DC-coupling AC-coupling C0 C3 4*C2 Zin≈0 Zin/4≈0 Q d =U1*C0 Discharge trajectory C0 C3 4*C2 C1 Zin≈0 Zin/4≈0 R1 Q d =U1*C5 Discharge trajectory C5=C0*C1/(C0+C1) ≈ C1 C1 C0 i(t) C0 C34*C2 Zin≈0 Zin/4≈0 i 1 (t) i in (t) i(t) C0 C3 4*C2 C1 Zin≈0 Zin/4≈0 i 1 (t) i in (t) R1 In order to collect much of the charge i in (t) ≈ i(t) the following condition must be met C1 C3+4*C2. For better safety C1 0. Therefore values of the parasitic capacitors C3,C4 are important to know. Signal collection DC-coupling AC-coupling

C=1.8fF when R=25um, d=50um Pad-to-Micromegas grid capacitance calculations. R - is a radius of the pad. The pad is a circle. d - is pad-to-Micromegas distance.  0 - is vacuum dielectric constant. D Ideal boundless plane Ideal uniformly charged disk R

C=0.62fF when b=30um, a=20um, pitch=50um Conclusion: C3+4*C2 = 1.8fF +4*0.62fF = 4.32fF Conclusion: C3+4*C2 = 1.8fF +4*0.62fF = 4.32fF In order to collect much of the charge i in (t) ≈ i(t) the following condition must be met C1 4fF a b b Ideal uniformly charged square pad b - is length of the pad. The pad is a squire. 50um is a pitch [50um-b] - is a pad-to-pad distance.  0 - is vacuum dielectric constant.  r=4 - is relative permittivity of the dielectric. Pad-to-Pad capacitance calculations.

Input Output T249 Id= -1u Gm = 2.4u Gds = 26n Vgs= -963mV Vds=-957mV (Vds_sat=-658mV) Cgg= 57.7fF Cdd+Cjd=0.451fF+0.150fF=0.6f T245 Id= 1u Gm = 23.2u Gds = 0.7u Vgs= 234mV Vds=243mV (Vds_sat=45mV) Cgg= 2.6fF Cdg=0.8fF Cdd+Cjd=0.8fF+0.7fF=1.5f Schematic of the Preamplifier. Main specifications. Technology: 0.13um CMOS. Power supply voltage:1.2V Power consumption: 1uA * 1.2V = 1.2uW. Charge sensitivity (real detector current pulse): 33mv/448e. Shaping function: rise time is 6ns, decay time is 100ns. Output noise (RMS): 4.3mV Equivalent input noise (RMS): (4.3mV/33mV)*448e = 58e  Cdg=0.8fF 100MΩ Idc=6nA

Input signal is a current δ-pulse Output signal as a response to the δ- pulse Input signal is a real current pulse Output signal as a response to the real current pulse Spectral density of the squire of the noise output voltage |V 2 n (jw)| 18.5uV 2 4.3mV The preamplifier. Simulation results.

Input Output Idc The preamplifier. Monte-Carlo analysis in Affirma Spectre. Channel-to- channel variations of the bias current Inom=1uA σ=5% Channel-to- channel variations of output voltage Unom=247mV σ=6.5% Channel-to-channel variations of gain (charge sensitivity) GAINnom=33mV/448e σ=8.7%

Schematic of the Preamp + Shaper + Discriminator. Main specifications. Technology: 0.13um CMOS. Power supply voltage:1.2V Power consumption: 1.6uA * 1.2V = 1.92uW (3.3*10 6 channels per wafer or 6.3W per wafer). Charge sensitivity (real detector current pulse at the shaper output): 254mv/448e. Shaping function: rise time is 23ns, decay time is 100ns. Output noise (RMS): 37mV Equivalent input noise (RMS) at the shaper’s output: (37mV/254mV)*448e = 65e Input Output 240nA 100nA 300nA 1000nA

Input current Preamp output Shaper output + threshold Output of the first stage of the discriminator Output of the discriminator Channel-to-channel gain variations at the output of the shaper GAINnom=254mV/448e σ=10% Channel-to-channel variations of the voltage at the output of the shaper σ = 18mV Uthr=190mV. Preamplifier + Shaper + Discriminator. Simulation results and Monte-Carlo analysis in Affirma Spectre.

Walk-time as a function of the signal amplitude (THR=448e) 0.8*448e 1*448e 1.5*448e 2*448e 3*448e 5*448e 12*448e 20*448e 50*448e Preamplifier + Shaper + Discriminator. Statistical analysis.

Time-walk vs pulse height distribution Signal, electrons THR=448e Gain=8000 Gain=4000 Gain=2000 Time-walk curve time,ns Entries efficiency=100% Time resolution (time distribution of the threshold crossing events). Statistics is Gain = 8000 Gain = 4000 Gain = 2000 Preamplifier + Shaper + Discriminator. Statistical analysis. Time resolution !!! It is feasible to reach time resolution of order of σ=2ns (100um) with a realistic gas gain.

Phase detector Clk 40MHz Delay chain. DLL #1 #2 #3#4 #16 Block diagram of the DLL.

Vdd=1.2V bias1 bias2 bias3 In + In - Out+ Out- An inverter in low-voltage current-steering logic. ±200mV

Conclusion..The TimePix detector is going to be a powerful tool for future experiments.. Definition of the topology and specifications of the detector is in progress on the basis of the potentialities of the modern deep sub-micron CMOS technology. The following specification have been found feasible so far: Gas gain: Single electron efficiency: 80%-94%. Input referred threshold: 500e. Time resolution: σ = 2ns corresponding to spatial resolution σ = 100um. Power dissipation: 3.2uW/channel (10W/wafer). AC coupling to the preamplifier looks preferable from safety point of view. Not much of the signal will be lost if the coupling capacitor is as tiny as 30fF…40fF..First trial to design an analog circuit in the 0.13um CMOS technology capable to meet the specification has shown a promising result.. DLL-based TDC structure is a possible candidate for time-to-digital conversion block.. More efforts needs to be made to design switching noise free logic cells.