Sp09 CMPEN 411 L18 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 16: Static Sequential Circuits [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

Sp09 CMPEN 411 L18 S.2 A Chip Example Type Gate_Count Area NAND AND OR NOR XOR XNOR INV MUX REG MEM OA AO ADD total gate count total gate count for combinatorial total area 23,766,927 um2 total area for combinatorial 3,091,530 um2 87% of the area are memory and registers

Sp09 CMPEN 411 L18 S.3 Sequential Logic Combinational Logic clock Outputs State Registers Next State Current State Inputs

Sp09 CMPEN 411 L18 S.4 Timing Metrics clock In Out data stable output stable output stable time clock D Q In Out t su t hold t c-q

Sp09 CMPEN 411 L18 S.5 System Timing Constraints Combinational Logic clock Outputs State Registers Next State Current State Inputs T  t c-q + t plogic + t su t cdreg + t cdlogic  t hold T (clock period)

Sp09 CMPEN 411 L18 S.6 Static vs Dynamic Storage  Static storage l preserve state as long as the power is on l have positive feedback (regeneration) with an internal connection between the output and the input l useful when updates are infrequent (clock gating)  Dynamic storage l store state on parasitic capacitors l only hold state for short periods of time (milliseconds) l require periodic refresh l usually simpler, so higher speed and lower power

Sp09 CMPEN 411 L18 S.7 Latches vs Flipflops  Latches l level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode l input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode  Flipflops (edge-triggered) l edge sensitive circuits that sample the inputs on a clock transition -positive edge-triggered: 0  1 -negative edge-triggered: 1  0 l built using latches (e.g., master-slave flipflops)

Sp09 CMPEN 411 L18 S.8 Positive and Negative Latches clock D Q In Out clock D Q In Out clk Out In clk Out In

Sp09 CMPEN 411 L18 S.9 Review: The Regenerative Property If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point. A V i2 V o2 V i1 = V o2 V i2 = V o1 B C V o1 V i1 cascaded inverters

Sp09 CMPEN 411 L18 S.10 Bistable Circuits  The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)  Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1 l done by applying a trigger pulse at V i1 or V i2 l the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter)  Two approaches used l cutting the feedback loop (mux based latch) l overpowering the feedback loop (as used in SRAMs) V i1 V i2

Sp09 CMPEN 411 L18 S.11 Bistable Circuits  The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)  Have to be able to change the stored  Two approaches used l cutting the feedback loop (mux based latch) l overpowering the feedback loop (as used in SRAMs) V i1 V i2

Sp09 CMPEN 411 L18 S.12 Review (from CSE 271): SR Latch SRQ!Q 00Q memory 1010set 0101reset 1100disallowed S R Q !Q

Sp09 CMPEN 411 L18 S.13 Review (from CSE 271): Clocked D Latch clock D Latch QD D Q !Q clock transparent mode hold mode

Sp09 CMPEN 411 L18 S.14 MUX Based Latches Q D clk 0 1 Positive Latch Q D clk 1 0 Negative Latch Q = !clk & Q | clk & D Q = clk & Q | !clk & D feedback transparent when the clock is low transparent when the clock is high feedback  Change the stored value by cutting the feedback loop

Sp09 CMPEN 411 L18 S.15 TG MUX Based Latch Implementation Q D clk !clk clk input sampled (transparent mode) feedback (hold mode) clk D Latch QD

Sp09 CMPEN 411 L18 S.16 PT MUX Based Latch Implementation Q D clk!Q !clk clk input sampled (transparent mode) feedback (hold mode)  Reduced area and clock load, but a threshold drop at output of pass transistors so reduced noise margins and performance

Sp09 CMPEN 411 L18 S.17 Latch Race Problem Combinational Logic clk State Registers clk BB’ Two-sided clock constraint T  t c-q + t plogic + t su T high  t c-q + t cdlogic B Which value of B is stored?

Sp09 CMPEN 411 L18 S.18 Master Slave Based ET Flipflop QMQM D0 1Q 1 0 Slave Master QMQM D clk 0 1Q 1 0 Slave Master clk QMQM Q D clock D FF QD clk = 0 transparent hold clk = 0  1 hold transparent

Sp09 CMPEN 411 L18 S.19 MS ET Implementation Q D clk QMQM I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 T2T2 T1T1 T3T3 T4T4 Master Slave!clk clk

Sp09 CMPEN 411 L18 S.20 MS ET Implementation Q D clk QMQM I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 T2T2 T1T1 T3T3 T4T4 Master Slave!clk clk master transparent slave hold master hold slave transparent

Sp09 CMPEN 411 L18 S.21 MS ET Timing Properties  Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0  Set-up time - time before rising edge of clk that D must be valid  Propagation delay - time for Q M to reach Q  Hold time - time D must be stable after rising edge of clk -

Sp09 CMPEN 411 L18 S.22 MS ET Timing Properties  Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0  Set-up time - time before rising edge of clk that D must be valid  Propagation delay - time for Q M to reach Q  Hold time - time D must be stable after rising edge of clk t su = 3 * t pd_inv + t pd_tx t c-q = t pd_inv + t pd_tx t hold = zero

Sp09 CMPEN 411 L18 S.23 Set-up Time Simulation Volts Time (ns) D clk Q QMQM I 2 out t su = 0.21 ns works correctly t setup

Sp09 CMPEN 411 L18 S.24 Set-up Time Simulation Volts Time (ns) D clk Q QMQM I 2 out t su = 0.20 ns fails t setup

Sp09 CMPEN 411 L18 S.25 Propagation Delay Simulation Volts Time (ns) t c-q(LH) = 160 psec t c-q(HL) = 180 psect c-q(LH) t c-q(HL)

Sp09 CMPEN 411 L18 S.26 Power PC Flipflop D Q !clk clk !clk clk

Sp09 CMPEN 411 L18 S.27 Power PC Flipflop D Q !clk clk !clk clk master transparent slave hold master hold slave transparent 00 11 00 11

Sp09 CMPEN 411 L18 S.28 Reduced Load MS ET FF !clkclk Q D !clkclk I1I1 I2I2 I4I4 I3I3 QMQM T2T2 T1T1 reverse conduction  Clock load per register is important since it directly impacts the power dissipation of the clock network.  Can reduce the clock load (at the cost of robustness) by making the circuit ratioed l to switch the state of the master, T 1 must be sized to overpower I 2 l to avoid reverse conduction, I 4 must be weaker than I 1

Sp09 CMPEN 411 L18 S.29 Non-Ideal Clocks 1-1 overlap 0-0 overlap !clk clk Ideal clocks !clk clk Non-ideal clocks clock skew

Sp09 CMPEN 411 L18 S.30 Example of Clock Skew Problems D clk X !clk !Q !clkQ clk B A P1P1 P2P2 P3P3 P4P4 I1I1 I2I2 I3I3 I4I4 Race condition – direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap) Undefined state – both B and D are driving A when clk and !clk are both high Dynamic storage – when clk and !clk are both low (0-0 overlap)

Sp09 CMPEN 411 L18 S.31 Pseudostatic Two-Phase ET FF D clk1 X clk2 !Q clk2Q clk1 B A P1P1 P2P2 P3P3 P4P4 I1I1 I2I2 I3I3 I4I4 clk2 clk1 master transparent slave hold master hold slave transparent dynamic storage t non_overlap

Sp09 CMPEN 411 L18 S.32 Two Phase Clock Generator clk clk1 clk2 A clk A B B clk1 clk2

Sp09 CMPEN 411 L18 S.33 Review (from CSE 271): SR Latch SRQ!Q 00Q memory 1010set 0101reset 1100disallowed S R Q !Q

Sp09 CMPEN 411 L18 S.34 Review (from CSE 271): Clocked D Latch clock D Latch QD D Q !Q clock transparent mode hold mode

Sp09 CMPEN 411 L18 S.35 Ratioed CMOS Clocked SR Latch onoff on off on M1 S R clk !Q Q M2 M3 M4 M5 M6 M7 M8

Sp09 CMPEN 411 L18 S.36 Ratioed CMOS Clocked SR Latch onoff off  on  0 1  on off on  on  off M1 S R clk !Q Q M2 M3 M4 M5 M6 M7 M8 0  1

Sp09 CMPEN 411 L18 S.37 Sizing Issues W/L 5and6 !Q (Volts) W/L 2and4 = 1.5  m/0.25  m W/L 1and3 = 0.5  m/0.25  m so W/L 5and6 > 3

Sp09 CMPEN 411 L18 S.38 Transient Response Q & !Q (Volts) SET !Q Q Time (ns) t c-!Q t c-Q

Sp09 CMPEN 411 L18 S.39 6 Transistor CMOS SR Latch clk S R M1 S R clk !Q Q M2 M3 M4 M5 M6 clk Will see this structure in SRAM design

Sp09 CMPEN 411 L18 S.40 Next Lecture and Reminders  Next lecture l Dynamic sequential circuits -Reading assignment – Rabaey, et al, 7.3, 7.7