ESA Workshop: on a harmonized mixed-signal flow Gilles Foucard EN/STI/ECE

Outline  Introduction  Project presentation  Roadmap  Current status  Conclusions

Introduction  Workshop that took place at ESTEC on the 29/01/2015. CERN invited as observer.  Digital ASICs  Mature solutions exist  Generic development & qualification is straightforward  Analogue & Mixed-signal ASICs  Involves varying consortium of companies  Development efforts are repeated  Long time development + risk of failure at late stage of the project  No ESCC (European Space Components Coordination) qualified mixed-signal ASIC technology  No ESCC qualified mixed-signal ASIC supply chain available today ITT (Invitation To Tender) AO7794 : Harmonized Mixed-Signal ASIC Flow

AO7794 in brief  Topic: Evaluation and characterization of a harmonized mixed- signal ASIC flow  Prime Contractor: ISD SA (GR). Integrated Systems Development  Sub-contractors:  Atmel France: no ITAR or any USA restrictions on their products  Airbus  VTT Technical Research Center of Finland Ltd (FI)  CSL (B) Centre Spatial de Liège  2 nd level sub-contractors:  Astri Polska (PL)  Duration: 2 years  Kick-off meeting: October 2014

Scope and Expected Outcomes  Propose solutions that will allow hardened Mixed-Signal ASICs to be realized. This includes:  Hardened design kits  Hardened design rules  Adequate design flow (full Digital, full analogue, Analogue on top or Digital on top)  Library of pre-qualified analogue and mixed functional-blocks that can be used in future designs  Propose an ecosystem able to deliver hardened ASICs  A business model  A supply chain  Project based on the digital 180nm (ATC18RHA) technology from Atmel converted to 150nm. Then, add mixed-signal features, high-voltage, 5V IO compatibility, etc

ITT requirements  Process features  CMOS based  Number of metal layers: >=5  Number of poly layers: >=1  Capability for 5V compatible IO pads  Gate density of RH digital library : >5 kgates/mm²  Operating temperature range: -55C….125C  ESD level: HBM 2kV (target 4 kV)  HV capability (devices): (target >=28V)  Radiation requirements  Capability of a SEL free (LET of 60 MeV-cm2/mg, TID up to 100 krad) RH digital library  Digital library and analogue blocks must be SEL free at an LET of 60 MeV-cm2/mg.  Parameter drifts shall stay within specification at a minimal TID level of 100 krad.  Analogue features and memory  Capability of high density single and dual port SRAM memories (target>32 kbytes)  Capability of Embedded NVM (target >32kbit)  Capability of RH ADC and DAC with >10bit ENOB at >100kSps (target ADC/DAC operating at 100kSps/16ENOB, 1MSps/14ENOB, 10MSps/12ENOB and 100MSps/10ENOB)  Capability of >100MHz RH PLL  Quality aspects  Commercially qualified (automotive, consumer, wireless, etc.) baseline  Qualification capability of the flow: ESCC QML or QPL  Reliability/lifetime of components > 15 years

Project phases Project in two phases:  Phase 1  Task 1: Requirements review and consolidation (now)  Task 2: Analogue and Mixed-Signal Design Kit for space ASICs  Phase 2  Task 3: Design of evaluation test chip(s)  Task 4: Manufacturing, packaging, electrical testing  Task 5: Evaluation testing, radiation testing

Project roadmap Adapt digital 180nm ATC18RHA to 150nm + 5V IO compatibility => ATMX150RHA digital 5V 300MHz) Functional & radiation tests of ATMX150RHA digital Extended ATMX150RHA digital 300MHz) 15Q4: ATMX150RHA digital ready for flight 16Q1-4: Extended ATMX150RHA digital + radhard Analogue library Q4: Kick-off 14Q4->15Q1: Requirement review & consolidation 15Q2->Q3: Analogue & Mixed-Signal design kit for space ASICs 15Q3->16Q1: Detailed design of the evaluation test chips 16Q1->Q3: Manufacturing, packaging & electrical testing 16Q3->Q4: Radiation testing Atmel AO7794

Proposed IPs by Atmel & ISD FamilyFeaturesAvailability PLL MHz programmable VCONow, already used in ATC18RHA PLL MHz programmable VCOExists Xtal OSC 10MHz RC oscillatorExists Xtal OSC 45MHz RC oscillatorExists Xtal OSC Up to 20MHz – 1.8V – accuracy < 1%16Q1 (pre-qualified by Atmel) ADC 12bit 2MspsExists (hardened) ADC ΣΔ 24bit ΣΔ low-speed (96ksps)16Q1 (pre-qualified by Atmel) DAC 10bitExists DAC ΣΔ 24bit ΣΔ low-speed low-power (300ksps)16Q1 (pre-qualified by Atmel) Vcomp. Voltage comparator, supply=3.3V, (pre-qualified by Atmel) Vref Voltage reference, supply=3.3V, output: 1.21V/1.23V,1.26VExists MUX 8-channel Multiplexer 8:1Exists Vreg LDO Voltage regulator 5V down to 2.7V – Output 1.8V – 700mV Dropout Voltage – Now Conv DC-DC converter – 5V -> 2.5V – 300mA16Q1 (pre-qualified by Atmel) POR Power-On-Reset – Supply = 1.8V – Vth = 0.9V16Q1 (pre-qualified by Atmel)

Features & IPs requested by the partners  TESAT  MOSFET driver stage  Non-volatile memory  Capability to handle higher input voltages  RUAG  10 to 50MHz small digital ASICs (data handling)  100 to 400MHz large digital ASICs (signal processing)  Airbus  Fast ADC (13 bits - 20MHz) & DAC (15 bits - 10MHz)  Fast, low offset AOP

Conclusions  This project aims at proposing tools and methodologies for companies to design their own analogue & mixed-signal integrated circuit based on:  Design kit  Design flow  Pre-qualified analogue and mixed-signal IP blocks  Project at its early stage (kick-off October 2014)  Current stage:  Selection of IPs to be Pre-qualified  Business model definition  Major identified problem: how to test analogue & mixed-signal blocks in an integrated circuit?

Thank you for your attention Any questions?