Z. Feng MTU EE480 14.1 EE4800 Fall 2011 CMOS Digital IC Design & Analysis Lecture 14 Final Exam Review Zhuo Feng.

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Presentation transcript:

Z. Feng MTU EE EE4800 Fall 2011 CMOS Digital IC Design & Analysis Lecture 14 Final Exam Review Zhuo Feng

Z. Feng MTU EE ■ Final Exam Time ► December 13 th ► 90 minutes: 13:00-14:30 ■ Five problems ► Covers the latest five lectures ■ One A4-size cheat sheet ■ No lecture slides or textbooks allowed

Z. Feng MTU EE ■ Interconnect ► Wire resistance ► Parasitic capacitance ► Cross talk noise ► Wire engineering ■ Combinational Circuit ► Bubble pushing ► Logic effort calculation ► Input order ► Skewed gates ► Asymmetric gate

Z. Feng MTU EE ■ Sequential Circuits ► Flip-flop, latches ► Clock period ► Max-delay constraints (setup time constraints) ► Min-delay constraints (hold time constraints) ► Clock skew ■ 6T SRAM Cell ► Read operation ► Write operation ► Transistor sizing ► Decoder ► Bitline Conditioning ■ Packaging, power distribution and clock distributions